Directed interrupt virtualization with blocking indicator

Patent metadata

Field	Value
Publication number	US-11023398-B2
Application number	US-202016789567-A
Country	US
Kind code	B2
Filing date	Feb 13, 2020
Priority date	Feb 14, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

First claim

What is claimed is:

1. A computer program product for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the guest operating system, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
receiving, by a bus attachment device from a bus connected module of a plurality of bus connected modules operationally coupled to the plurality of processors via the bus attachment device, an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors assigned for usage by the guest operating system as a target processor to handle the interrupt signal;
retrieving, by the bus attachment device, a first copy of an interrupt table entry assigned to the interrupt target ID from an interrupt table, the first copy of the interrupt table entry comprising an interrupt blocking indicator indicating whether the target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals;
checking, by the bus attachment device, using the interrupt blocking indicator whether the target processor is blocked from receiving interrupt signals;
translating, by the bus attachment device based on the target processor being unblocked, the interrupt target ID to a logical processor ID, and forwarding the interrupt signal to the target processor to handle based on the target processor being unblocked and based on the target processor being scheduled for usage by the guest operating system as indicated by a running indicator separate from the interrupt blocking indicator, the forwarding using the logical processor ID resulting from the translating to address the target processor directly; and
blocking, by the bus attachment device based on the target processor being blocked, the interrupt signal from being forwarded to the target processor for handling.

2. The computer program product of claim 1 , wherein the method further comprises forwarding, by the bus attachment device, the interrupt signal for handling to remaining processors of the plurality of processors using broadcasting.

3. The computer program product of claim 1 , wherein the method further comprises:
checking, by an interrupt handler of the guest operating system, whether an interrupt addressed to the target processor is pending for handling by the target processor; and
changing, by the guest operating system based on no interrupt addressed to the target processor being pending for handling by the target processor, the interrupt blocking indicator in the first copy of the interrupt table entry, assigned to the target processor to indicate the target processor is unblocked.

4. The computer program product of claim 1 , wherein the interrupt blocking indicator is implemented as a single bit.

5. The computer program product of claim 1 , wherein the first copy of the interrupt table entry further comprises a mapping of the interrupt target ID to the logical processor ID, and wherein the translating comprises using, by the bus attachment device, the first copy of the interrupt table entry to translate the interrupt target ID to the logical processor ID of the target processor.

6. The computer program product of claim 1 , wherein the first copy of the interrupt table entry further comprises a copy of the running indicator indicating whether the target processor identified by the interrupt target ID is scheduled for usage by the guest operating system, and wherein the method further comprises;
checking, by the bus attachment device using the copy of the running indicator, whether the target processor is scheduled for usage by the guest operating system; and
forwarding, by the bus attachment device, the interrupt signal for handling to the plurality of processors using broadcasting, based on the target processor being unscheduled.

7. The computer program product of claim 1 , wherein the method further comprises changing, by the bus attachment device based on the target processor being unblocked, the interrupt blocking indicator in the first copy of the interrupt table entry assigned to the interrupt target ID to indicate the logical processor ID is blocked, wherein the changing is performed before the forwarding of the interrupt signal to the target processor to handle.

8. The computer program product of claim 7 , wherein the method further comprises:
retrieving, by the bus attachment device after the changing of the interrupt blocking indicator, a second copy of the interrupt table entry assigned to the interrupt target ID; and
checking, by the bus attachment device, the second copy of the interrupt table entry to exclude a predefined type of change of the second copy of the interrupt table entry relative to the first copy of the interrupt table entry, wherein the forwarding of the interrupt signal to the target processor for handling is performed, based on a successful exclusion of the predefined type of change.

9. The computer program product of claim 1 , wherein the method further comprises:
retrieving, by the bus attachment device, a copy of a device table entry from a device table, the copy of the device table entry comprising a direct signaling indicator indicating whether the target processor is to be addressed directly;
forwarding, based on the direct signaling indicator indicating a direct forwarding of the interrupt signal, the interrupt signal using the logical processor ID of the target processor to address the target processor directly; and
forwarding, by the bus attachment device based on the direct signaling indicator not indicating the direct forwarding, the interrupt signal for handling to the plurality of processors using broadcasting.

10. The computer program product of claim 1 , wherein the method further comprises:
retrieving, by the bus attachment device, a copy of a device table entry from a device table, the copy of the device table entry comprising an interrupt signal vector address indicator indicating a memory address of an interrupt signal vector, the interrupt signal vector comprising one or more interrupt signal indicators;
using, by the bus attachment device, the memory address of the interrupt signal vector to select an interrupt signal indicator of the one or more interrupt signal indicators that is assigned to the bus connected module which issued the interrupt signal addressed to the interrupt target ID; and
updating the interrupt signal indicator that is selected such that the interrupt signal indicator indicates that there is the interrupt signal issued by the bus connected module addressed to the interrupt target ID to be handled.

11. The computer program product of claim 1 , wherein the method further comprises:
retrieving a copy of a device table entry from a device table, the copy of the device table entry comprising an interrupt summary vector address indicator indicating a memory address of an interrupt summary vector, the interrupt summary vector comprising an interrupt summary indicator per bus connected module, each interrupt summary indicator being assigned to a respective bus connected module indicating whether there is a respective interrupt signal issued by the respective bus connected module to be handled; and
using, by the bus attachment device, the memory address of the interrupt summary vector to update a respective interrupt summary indicator assigned to the respective bus connected module from which the respective interrupt signal is received such that the respecti

Assignees

• IBM

Inventors

• Raisch Christoph
• Kraemer Marco
• Schmidt Donald William
• Nerz Bernd
• Junghans Sascha
• Driever Peter Dana

Classifications

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title