MSI events using dynamic memory monitoring

US10078603B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10078603-B2
Application numberUS-201213689950-A
CountryUS
Kind codeB2
Filing dateNov 30, 2012
Priority dateNov 30, 2012
Publication dateSep 18, 2018
Grant dateSep 18, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method and system for managing message-signaled interrupt-based events sent from an event source to a host or a guest is disclosed. A central processing unit instructs an event source to write a message-signaled interrupt to a designated address of a random access memory of the host. The host or a guest of the central processing unit executes a memory monitoring instruction to the designated address. The host or the guest enters a wait state. The host or the guest detects a write of the message-signaled interrupt by the event source to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed. The host or the guest exits from the wait state. The host or the guest performs an atomic operation with respect to the event based on the data items in the message-signaled interrupt.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: instructing, by a central processing unit, an event source of a set of event sources to write a message-signaled interrupt to a designated address of a random access memory of a host, wherein the set of event sources is selected from a plurality of event sources raising corresponding events for writing message-signaled interrupts to the designated address in view of counting a number of events originating from each of the plurality of event sources, and wherein a remaining set of event sources of the plurality of event sources is selected for writing a message-signaled table to a programmable interrupt controller associated with the host; executing a memory monitoring instruction to the designated address of the random access memory of the host; entering a wait state; and detecting a write of the message-signaled interrupt by the event source directly to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed. 2. The method of claim 1 , further comprising: exiting from the wait state; and performing an atomic operation with respect to the event in view of the data items in the message-signaled interrupt. 3. The method of claim 2 , wherein the memory monitoring instruction is by a guest associated with the host. 4. The method of claim 2 , wherein the memory monitoring instruction is by the host. 5. The method of claim 1 , wherein the designated address is in guest memory. 6. The method of claim 1 , wherein the designated address is in host memory. 7. The method of claim 2 , wherein instructing the event source to write the message-signaled interrupt to the designated address occurs prior to or following the execution of the memory monitoring to the designated address. 8. The method of claim 1 , wherein the message-signaled interrupt is an MSI interrupt or an MSI-X interrupt. 9. The method of claim 2 , wherein the atomic operation comprises concurrently reading the designated address to detect the event and clearing the event. 10. The method of claim 9 , wherein the atomic operation is one of a compare and exchange operation or a test and clear operation. 11. The method of claim 1 , wherein the selecting of the sets is in view of measuring a frequency of detected events from each of the plurality of event sources in view of counting a number of events originating from each of the plurality of event sources over a given period of time. 12. The method of claim 11 , further comprising: mapping events received from the event source to the designated address in response to the measured frequency of detected events from the event source is equal to or above a frequency threshold; and detecting events from an associated interrupt controller in response to the measured frequency of detected events from the event source is below the frequency threshold. 13. The method of claim 1 , wherein the event source is a hardware device of a host or a virtual device of a guest. 14. The method of claim 1 , wherein the event source is a PCI-based device. 15. A non-transitory computer readable storage medium comprising instructions that, when executed, cause a central processing unit to: instruct, by the central processing unit, an event source of a set of event sources to write a message-signaled interrupt to a designated address of a random access memory of a host, wherein the set of event sources is selected from a plurality of event sources raising corresponding events for writing message-signaled interrupts to the designated address in view of counting a number of events originating from each of the plurality of event sources, and wherein a remaining set of event sources of the plurality of event sources is selected for writing a message-signaled table to a programmable interrupt controller associated with the host; execute a memory monitoring instruction to the designated address of the random access memory of the host; enter a wait state; and detect a write of the message-signaled interrupt by the event source directly to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed. 16. The non-transitory computer readable storage medium of claim 15 , wherein the central processing unit is further to: exit from the wait state; and perform an atomic operation with respect to the event in view of the data items in the message-signaled interrupt. 17. A computer system comprising: a memory; a central processing unit, operatively coupled to the memory, the central processing unit to: instruct an event source of a set of event sources to write a message-signaled interrupt to a designated address of a random access memory of a host, wherein the set of event sources is selected for writing message-signaled interrupts to the designated address in view of counting a number of events originating from each of the plurality of event sources, and wherein a remaining set of event sources of the plurality of event sources is selected for writing a message-signaled table to a programmable interrupt controller associated with the host; and execute a memory monitoring instruction to the designated address of the random access memory of the host; enter a wait state; detect a write of the message-signaled interrupt by the event source directly to the designated address, the message-signaled interrupt comprising data items pertaining to an event to be performed. 18. The system of claim 17 , wherein the central processing unit further to: exit from the wait state; and perform an atomic operation with respect to the event in view of the data items in the message-signaled interrupt. 19. The non-transitory computer readable storage medium of claim 15 , wherein the selecting of the sets is in view of measuring a frequency of detected events from each of the plurality of event sources in view of counting a number of events originating from each of the plurality of event sources over a given period of time. 20. The system of claim 17 , wherein the selecting of the sets is in view of measuring a frequency of detected events from each of the plurality of event sources in view of counting a number of events originating from each of the plurality of event sources over a given period of time.

Assignees

Inventors

Classifications

  • G06F13/24Primary

    using interrupt (G06F13/32 takes precedence) · CPC title

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Frequently asked questions

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What does patent US10078603B2 cover?
A method and system for managing message-signaled interrupt-based events sent from an event source to a host or a guest is disclosed. A central processing unit instructs an event source to write a message-signaled interrupt to a designated address of a random access memory of the host. The host or a guest of the central processing unit executes a memory monitoring instruction to the designated …
Who is the assignee on this patent?
Red Hat Israel Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/24. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 18 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).