Planar cavity MEMS and related structures, methods of manufacture and design structures

US11021364B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11021364-B2
Application numberUS-201816031132-A
CountryUS
Kind codeB2
Filing dateJul 10, 2018
Priority dateJun 25, 2010
Publication dateJun 1, 2021
Grant dateJun 1, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

First claim

Opening claim text (preview).

What is claimed: 1. A method of forming at least one Micro-Electro-Mechanical System (MEMS), comprising: forming an insulator layer on a first sacrificial layer and a beam; forming a cavity via in the insulator layer, exposing a portion of the first sacrificial layer; forming an electrode on the insulator layer; forming a second sacrificial layer over the beam and in the cavity via; forming a lid material over the second sacrificial layer and the electrode; providing a vent hole in the lid material to expose at least the second sacrificial layer and forming a partial via over the electrode; venting the first sacrificial layer and the second sacrificial layer to form at least a lower cavity and an upper cavity, respectively; and forming a final via through the lid material by etching the lid material through the partial via, to the electrode, wherein the partial via is formed at a same time as the vent hole, and wherein the vent hole is provided greater than 5 microns away from both the partial via and the final via. 2. The method of claim 1 , wherein the beam and the upper cavity are remote from the electrode. 3. The method of claim 1 , wherein the vent hole is rounded or chamfered. 4. The method of claim 1 , wherein the vent hole is octagonal. 5. The method of claim 1 , wherein the first sacrificial layer and the second sacrificial layer are silicon layers. 6. The method of claim 1 , wherein the final via is formed by using two separate patterning and etching steps. 7. The method of claim 1 , further comprising forming the first sacrificial layer over discrete wires. 8. The method of claim 1 , further comprising performing a hafnium clean to remove oxide and hydrogen on exposed surfaces of the first sacrificial layer and the second sacrificial layer prior to venting the first sacrificial layer and the second sacrificial layer. 9. The method of claim 8 , wherein the venting the first sacrificial layer and the second sacrificial layer is selective to silicon dioxide. 10. The method of claim 1 , wherein the providing the vent hole in the lid material to expose at least the second sacrificial layer occurs simultaneously with the forming the partial via over the electrode. 11. A method of forming at least one Micro-Electro-Mechanical System (MEMS), comprising: forming an insulator layer on a first sacrificial layer and a beam; forming a cavity via in the insulator layer, exposing a portion of the first sacrificial layer; forming an electrode on the insulator layer; forming a second sacrificial layer over the beam and in the cavity via; forming a lid over the second sacrificial layer and the electrode; providing a vent hole in the lid to expose at least the second sacrificial layer and forming a partial via over the electrode; and etching the partial via to form a final via to expose an underlying electrode, wherein the final via is formed by using two separate patterning and etching steps, which reduces an etching time to expose the electrode. 12. The method of claim 11 , wherein the final via has a tapered angle. 13. The method of claim 11 , wherein the partial via has a larger cross section than an underlying via which results in the final via. 14. The method of claim 11 , wherein the underlying electrode is composed of Ti/AlCu/Ti/Tn and is formed over an insulator layer. 15. The method of claim 11 , wherein the vent holes are provided greater than 5 microns away from both the partial via and the final via. 16. The method of claim 11 , further comprising venting the first sacrificial layer and the second sacrificial layer to form at least a lower cavity and an upper cavity, respectively, and the first sacrificial layer and the second sacrificial layer are silicon material vented using a XeF 2 etchant through the vent hole. 17. The method of claim 16 , wherein the vent hole is over the upper cavity such that the upper cavity vents before the lower cavity. 18. The method of claim 11 , further comprising: sealing the vent hole with material, the material comprises dielectric material and a nitride cap; and forming a polyimide material on the nitride cap, wherein the dielectric material, the nitride cap, and the polymide material are formed in the partial via. 19. The method of claim 11 , wherein the lower cavity and the upper cavity have at least one chamfered cavity corner to reduce stress after the venting. 20. The method of claim 11 , further comprising forming the final via through the lid by etching the lid through the partial via, to the electrode, and the providing the vent hole in the lid to expose at least the second sacrificial layer occurs simultaneously with the forming the partial via over the electrode.

Assignees

Inventors

Classifications

  • making use of micromechanics · CPC title

  • Switches making use of microelectromechanical systems [MEMS] (for electromagnetic relays H01H50/005; for electrostatic relays H01H59/0009) · CPC title

  • Creating layers of material on a substrate · CPC title

  • Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators · CPC title

  • Electrostrictive relays; Piezoelectric relays · CPC title

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What does patent US11021364B2 cover?
A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification B81C1/00476. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).