Differential clock level translator for charge pumps

Patent metadata

Field	Value
Publication number	US-11011981-B1
Application number	US-202017010060-A
Country	US
Kind code	B1
Filing date	Sep 2, 2020
Priority date	Sep 2, 2020
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

Circuits and methods for improved clock signal level shifting in charge pumps that avoids shoot-through current and loss due to simultaneous switching, which may be powered by V IN or any available level of V DD , and which provides a high level of clock signal voltage swing. Embodiments include a non-overlapping clock generator that generates a set of separate non-overlapping clock signals that are applied to a differential clock level translator coupled to a charge pump. The differential clock level translator level shifts the set of non-overlapping clock signals to a set of level-shifted non-overlapping clock signals. The charge pump is configured to receive the sets of non-overlapping clock signals and apply them to corresponding NMOS and PMOS switches. The set of level-shifted non-overlapping clock signals have shifted voltages sufficient to switch corresponding switches having elevated source voltages V S . The charge pump may be a differential charge pump in some embodiments.

First claim

What is claimed is:

1. A differential clock level translator circuit configured to be coupled to a PMOS output-side charge pump switch and an NMOS output-side charge pump switch of a charge pump, the differential clock level translator circuit configured to generate a first level-shifted clock signal for the NMOS output-side charge pump switch in response to a second clock signal and a fourth clock signal, and to generate a second level-shifted clock signal for the PMOS output-side charge pump switch in response to a first clock signal and a third clock signal;
wherein the first clock signal is in a LOW state only when the second clock signal is already in the LOW state, and the second clock signal is in a HIGH state only when the first clock signal is already in the HIGH state, wherein the third clock signal is in the LOW state only when the fourth clock signal is already in the LOW state, and the fourth clock signal is in the HIGH state only when the third clock signal is already in the HIGH state, and wherein the first clock signal and the third clock signal cannot be in a LOW state simultaneously, and the second clock signal and the fourth clock signal cannot be in a HIGH state simultaneously.

2. The invention of claim 1 , wherein the first level-shifted clock signal has a low voltage level V LOW approximately equal in magnitude to the magnitude of an input voltage to the charge pump, and a high voltage level V HIGH approximately equal in magnitude to the magnitude of V LOW plus a voltage derived from a supply voltage to the non-overlapping clock generator minus some charge redistribution loss.

3. The invention of claim 1 , wherein the second level-shifted clock signal has a low voltage level V LOW approximately equal in magnitude to the magnitude of an output voltage of the charge pump minus a voltage derived from a supply voltage to the non-overlapping clock generator plus some charge redistribution loss, and a high voltage level V HIGH approximately equal in magnitude to the magnitude of the output voltage of the charge pump.

4. The invention of claim 1 , wherein the differential clock level translator circuit includes a PMOS clock latch including:
(a) a first capacitor coupled to the first clock signal;
(b) a second capacitor coupled to the third clock signal;
(c) a first PMOS FET having a drain-source channel coupled between the first capacitor and an output voltage of the charge pump when coupled, and having a gate coupled to the second capacitor;
(d) a second PMOS FET having a drain-source channel coupled between the second capacitor and the output voltage of the charge pump when coupled, and having a gate coupled to the first capacitor;
wherein the second level-shifted clock signal is output from a node between the first capacitor and the drain-source channel of the first PMOS FET.

5. The invention of claim 1 , wherein the differential clock level translator circuit includes an NMOS clock latch including:
(a) a first capacitor coupled to the second clock signal;
(b) a second capacitor coupled to the fourth clock signal;
(c) a first NMOS FET having a drain-source channel coupled between the first capacitor and an input voltage of the charge pump when coupled, and having a gate coupled to the second capacitor;
(d) a second NMOS FET having a drain-source channel coupled between the second capacitor and the input voltage of the charge pump when coupled, and having a gate coupled to the first capacitor;
wherein the first level-shifted clock signal is output from a node between the first capacitor and the drain-source channel of the first NMOS FET.

6. A voltage level shifting circuit configured to be coupled to a charge pump having a PMOS output-side charge pump switch and an NMOS output-side charge pump switch, including:
(a) a non-overlapping clock generator configured to output non-overlapping first and second clock signals, and non-overlapping third and fourth clock signals; and
(b) a differential clock level translator circuit, coupled to the non-overlapping clock generator and configured to be coupled to the PMOS output-side charge pump switch and the NMOS output-side charge pump switch of the charge pump, wherein the differential clock level translator circuit generates a first level-shifted clock signal for the NMOS output-side charge pump switch in response to the second and fourth clock signals, and wherein the differential clock level translator circuit generates a second level-shifted clock signal for the PMOS output-side charge pump switch in response to the first and third clock signals.

7. The invention of claim 6 , wherein the first level-shifted clock signal has a low voltage level V LOW approximately equal in magnitude to the magnitude of an input voltage to the charge pump, and a high voltage level V HIGH approximately equal in magnitude to the magnitude of V LOW plus a voltage derived from a supply voltage to the non-overlapping clock generator minus some charge redistribution loss.

8. The invention of claim 6 , wherein the second level-shifted clock signal has a low voltage level V LOW approximately equal in magnitude to the magnitude of an output voltage of the charge pump minus a voltage derived from a supply voltage to the non-overlapping clock generator plus some charge redistribution loss, and a high voltage level V HIGH approximately equal in magnitude to the magnitude of the output voltage of the charge pump.

9. The invention of claim 6 , wherein the differential clock level translator circuit includes a PMOS clock latch including:
(a) a first capacitor coupled to the first clock signal;
(b) a second capacitor coupled to the third clock signal;
(c) a first PMOS FET having a drain-source channel coupled between the first capacitor and an output voltage of the charge pump when coupled, and having a gate coupled to the second capacitor;
(d) a second PMOS FET having a drain-source channel coupled between the second capacitor and the output voltage of the charge pump when coupled, and having a gate coupled to the first capacitor;
wherein the second level-shifted clock signal is output from a node between the first capacitor and the drain-source channel of the first PMOS FET.

10. The invention of claim 6 , wherein the differential clock level translator circuit includes an NMOS clock latch including:
(a) a first capacitor coupled to the second clock signal;
(b) a second capacitor coupled to the fourth clock signal;
(c) a first NMOS FET having a drain-source channel coupled between the first capacitor and an input voltage of the charge pump when coupled, and having a gate coupled to the second capacitor;
(d) a second NMOS FET having a drain-source channel coupled between the second capacitor and the input voltage of the charge pump when coupled, and having a gate coupled to the first capacitor;
wherein the first level-shifted clock signal is output from a node between the first capacitor and the drain-source channel of the first NMOS FET.

11. A voltage level shifting circuit configured to be coupled to a charge pump having a PMOS output-side charge pump switch and an NMOS output-side charge pump switch, including:
(a) a non-overlapping clock generator configured to output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, each clock signal having a LOW state and a HIGH state, wherein the first clock signal is in the LOW state only when the second clock signal is already in the LOW state, and the second clock signal is in the HIGH state only when the first clock signal is already in the HIGH state, wherein the third clock signal is in the LOW state only when the fourth clock signal is already in the L

Assignees

• Psemi Corp

Inventors

• Englekirk Robert Mark

Classifications

• H02M1/38

  Means for preventing simultaneous conduction of switches · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H02M3/075

  including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages · CPC title

• H02M3/076

  the clock signals being boosted to a value being higher than the input voltage value · CPC title