Low-Noise High Efficiency Bias Generation Circuits and Method
US-2018046210-A1 · Feb 15, 2018 · US
US9998002B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9998002-B2 |
| Application number | US-201715670945-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 7, 2017 |
| Priority date | Jul 1, 2013 |
| Publication date | Jun 12, 2018 |
| Grant date | Jun 12, 2018 |
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A DC-to-DC voltage converter comprising a differential charge pump that utilizes a differential clocking scheme to reduce output electrical noise by partial cancellation of charge pump glitches (voltage transients), and a corresponding method of operating a differential charge pump. The differential charge pump can be characterized as having at least two charge pump sections that initiate charge pumping in opposite phases of a clock signal to transfer (pump) charge to storage capacitors. The differential charge pump is particularly well suited for implementation in integrated circuit chips requiring negative and/or positive voltages, and multiples of such voltages, based on a single input voltage.
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What is claimed is: 1. A differential charge pump, including: (a) a clock signal having a first phase and a second phase, the second phase being different from the first phase, for controlling switch devices regulating charge pumping cycles of the differential charge pump; (b) at least two charge pump sections electrically coupled in parallel to an input voltage source separate from the clock signal, wherein each charge pump section generates an output voltage different from an input voltage from the input voltage source, each charge pump section including at least two charge pumping stages having an input and an output, the input of each charge pumping stage being switchably coupled to an associated input voltage source separate from the clock signal and the output of each charge pumping stage being switchably coupled to one of (i) an associated intermediate storage capacitance coupled to and shared with at least one other of the at least two charge pump sections or (ii) a common terminal storage capacitance, each charge pumping stage including: (1) a fly capacitor having an input and an output; (2) a first switch device coupled between the input of the fly capacitor and an intermediate node, and coupled to and controlled by a selected one of the first phase or the second phase of the clock signal; and (3) a second switch device coupled between the intermediate node and the output of the fly capacitor, and coupled to and controlled by a selected one of the second phase or the first phase of the clock signal, the selected phase controlling the second switch device being different from the selected phase controlling the first switch device; wherein the charge pumping cycle in at least a first one of the charge pump sections is initiated on the first phase of the clock signal, and the charge pumping cycle in at least a second one of the charge pump sections is initiated on the second phase of the clock signal. 2. The invention of claim 1 , wherein the output of at least one charge pumping stage is switchably coupled to the associated intermediate storage capacitance coupled to and shared with at least one other of the at least two charge pump sections, and the output of at least one other charge pumping stage is switchably coupled to the common terminal storage capacitance. 3. The invention of claim 1 , wherein the output voltage of the charge pump is the opposite polarity with respect to the input voltage source. 4. The invention of claim 1 , wherein the output voltage of the charge pump is the same polarity with respect to the input voltage source. 5. The invention of claim 1 , wherein each charge pump section includes two charge pumping stages. 6. The invention of claim 1 , wherein each charge pump section includes at least three charge pumping stages. 7. The invention of claim 1 , wherein the first switch device and the second switch device of each charge pumping stage are field effect transistors. 8. The invention of claim 7 , wherein the first switch device and the second switch device of each charge pumping stage are MOSFETS. 9. The invention of claim 1 , wherein the differential charge pump is fabricated as at least part of an integrated circuit. 10. The invention of claim 9 , wherein the integrated circuit further includes additional circuitry other than the differential charge pump. 11. The invention of claim 10 , wherein the additional circuitry includes at least one radio frequency switch. 12. The invention of claim 1 , wherein the first phase and the second phase of the clock signal are non-overlapping. 13. A differential charge pump, including: (a) a clock signal having a first phase and a second phase, the second phase being different from the first phase, for controlling field effect transistor (FET) switch devices regulating charge pumping cycles of the differential charge pump; (b) at least two charge pump sections electrically coupled in parallel to an input voltage source separate from the clock signal, wherein each charge pump section generates an output voltage different from an input voltage from the input voltage source, each charge pump section including at least two charge pumping stages having an input and an output, the input of each charge pumping stage being switchably coupled to an associated input voltage source separate from the clock signal and the output of each charge pumping stage being switchably coupled to one of (i) an associated intermediate storage capacitance coupled to and shared with at least one other of the at least two charge pump sections or (ii) a common terminal storage capacitance, each charge pumping stage including: (1) a fly capacitor having an input and an output; (2) a first FET switch device coupled between the input of the fly capacitor and an intermediate node, and coupled to and controlled by a selected one of the first phase or the second phase of the clock signal; and (3) a second FET switch device coupled between the intermediate node and the output of the fly capacitor, and coupled to and controlled by a selected one of the second phase or the first phase of the clock signal, the selected phase controlling the second FET switch device being different from the selected phase controlling the first FET switch device; wherein the charge pumping cycle in at least a first one of the charge pump sections is initiated on the first phase of the clock signal, and the charge pumping cycle in at least a second one of the charge pump sections is initiated on the second phase of the clock signal; and wherein the differential charge pump is fabricated as at least part of a MOSFET integrated circuit that includes at least one radio frequency switch. 14. A method for operating a charge pump, including: (a) providing a clock signal having a first phase and a second phase, the second phase being different from the first phase, for controlling switch devices regulating charge pumping cycles of the charge pump; (b) providing at least two charge pump sections electrically coupled in parallel to an input voltage source separate from the clock signal, wherein each charge pump section generates an output voltage different from an input voltage from the input voltage source, each charge pump section including at least two charge pumping stages having an input and an output, the input of each charge pumping stage being switchably coupled to an associated input voltage source separate from the clock signal and the output of each charge pumping stage being switchably coupled to one of an associated intermediate storage capacitance coupled to and shared with at least one other of the at least two charge pump sections or a common terminal storage capacitance, each charge pumping stage including: (1) a fly capacitor having an input and an output; (2) a first switch device coupled between the input of the fly capacitor and an intermediate node, and coupled to and controlled by a selected one of the first phase or the second phase of the clock signal; and (3) a second switch device coupled between the intermediate node and the output of the fly capacitor, and coupled to and controlled by a selected one of the second phase or the first phase of the clock signal, the selected phase controlling the second switch device being different from the selected phase controlling the first switch device; (c) initiating a charge pumping cycle in at least a first one of the charge pump sections on the first phase of the clock signal; and (d) initiating a charge pumping cycle in at least a second one of the charge pump sections on the second phase of the clock signal. 15. The method of clai
using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title
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