Self-oscillating switched-capacitor DC-DC converter

Patent metadata

Field	Value
Publication number	US-9979284-B2
Application number	US-201515116072-A
Country	US
Kind code	B2
Filing date	Feb 5, 2015
Priority date	Feb 5, 2014
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A self-oscillating DC-DC converter structure is proposed in which an oscillator is completely internalized within the switched-capacitor network. This eliminates power overhead of clock generation and level shifting and enables higher efficiency at lower power levels. Voltage doublers are cascaded to form a complete energy harvester with a wide load range from 5 nW to 5 μW and self-starting operation down to 140 mV. Because each doubler is self-oscillating, the frequency of each stage can be independently modulated, thereby optimizing the overall conversion efficiency.

First claim

What is claimed is:

1. A self-oscillating DC-DC converter, comprising:
an upper ring oscillator comprised of n upper stages, each upper stage having an input node, an output node, a supply node, and a return node, where the supply node from each upper stage is electrically coupled together, the return node from each upper stage is electrically coupled to a common return line;
a lower ring oscillator comprised of n lower stages, each lower stage having an input node, an output node, a supply node, and a return node, where the supply node from each lower stage is electrically coupled to the common return line and the return node from each lower stage is electrically coupled together; and
at least one capacitor electrically coupled between an output node of a given upper stage and an output node in a corresponding lower stage,
wherein one or more delay elements are interposed between stages of the upper and lower ring oscillators.

2. The self-oscillating DC-DC converter of claim 1 wherein each stage in the upper ring oscillator and lower ring oscillator includes an inverter circuit and n is an odd integer greater than 2.

3. The self-oscillating DC-DC converter of claim 2 wherein each inverter circuit is further defined as a static CMOS inverter.

4. The self-oscillating DC-DC converter of claim 1 wherein each stage in the upper ring oscillator and lower ring oscillator includes one or more logic gates configured to perform an inverting function.

5. The self-oscillating DC-DC converter of claim 1 further comprises n capacitors electrically coupled between the upper ring oscillator and the lower ring oscillator, such that one capacitor is electrically connected between each output node of the upper stage and an output node of the corresponding lower stage.

6. The self-oscillating DC-DC converter of claim 1 wherein the supply nodes from the upper ring oscillator are coupled to a terminal configured to receive a first input voltage, the supply nodes from the lower ring oscillator are coupled to a terminal configured to receive a second input voltage and the return nodes from the lower ring oscillator are coupled to a terminal configured to receive a third input voltage, where the second input voltage is larger than the third input voltage and the first input voltage is larger than the second input voltage.

7. The self-oscillating DC-DC converter of claim 1 wherein the supply nodes from the lower ring oscillator are coupled to one input terminal for the lower ring oscillator and the return nodes from the lower ring oscillator are coupled to another input terminal for the lower ring oscillator such that the pair of input terminals are configured to receive an input voltage for driving the lower ring oscillator; and the supply nodes from the upper ring oscillator are coupled to one output terminal for the converter and the return nodes from the lower ring oscillator are coupled to another output terminal for the converter such that the input voltage is upconverted to an output voltage measured across the pair of output terminals.

8. The self-oscillating DC-DC converter of claim 1 wherein the supply nodes from the upper ring oscillator are coupled to one input terminal for the converter and the return node from the lower ring oscillator are coupled to another input terminal for the converter such that the pair of input terminals are configured to receive an input voltage; and the supply nodes from the lower ring oscillator are coupled to one output terminal for the lower ring oscillator and the return nodes from the lower ring oscillator are coupled to another output terminal for the lower ring oscillator such the input voltage is downconverted to an output voltage measured across the pair of output terminals.

9. A self-oscillating DC-DC converter, comprising:
an upper oscillator comprised of n upper stages arranged in series, each upper stage having an input node, an output node, a supply node, and a return node, where the supply node from each upper stage is electrically coupled together, the return node from each upper stage is electrically coupled to a common return line, n is an odd integer greater than 2, and the output node of one stage is connected to the input node of the adjacent stage with the exception of the output node of the last stage which is connected to the input node of the first stage;
a lower oscillator comprised of n lower stages arranged in series, each lower stage having an input node, an output node, a supply node, and a return node, where the supply node from each lower stage is electrically coupled to the common return line and the return node from each lower stage is electrically coupled together, the output node of one stage is connected to the input node of the adjacent stage with the exception of the output node of the last stage which is connected to the input node of the first stage; and
n capacitors electrically coupled between the upper ring oscillator and the lower ring oscillator, such that one capacitor is electrically connected between each output node of the upper stage and an output node of the corresponding lower stage,
wherein one or more delay elements are interposed between stages of the upper and lower ring oscillators.

10. The self-oscillating DC-DC converter of claim 9 wherein each stage is implemented by an inverter circuit.

11. The self-oscillating DC-DC converter of claim 10 wherein each inverter circuit is further defined as a static CMOS inverter.

12. The self-oscillating DC-DC converter of claim 10 wherein each stage further includes a delay cell coupled to the inverter circuit.

13. The self-oscillating DC-DC converter of claim 9 wherein each stage includes one or more logic gates configured to perform an inverting function.

14. The self-oscillating DC-DC converter of claim 9 wherein the supply nodes from the upper oscillator are coupled to a terminal configured to receive a first input voltage, the supply nodes from the lower oscillator are coupled to a terminal configured to receive a second input voltage and the return nodes from the lower oscillator are coupled to a terminal configured to receive a third input voltage, where the second input voltage is larger than the third input voltage and the first input voltage is larger than the second input voltage.

15. The self-oscillating DC-DC converter of claim 9 wherein the supply nodes from the lower oscillator are coupled to one input terminal for the lower oscillator and the return nodes from the lower oscillator are coupled to another input terminal for the lower oscillator such that the pair of input terminals are configured to receive an input voltage for driving the lower oscillator; and the supply nodes from the upper oscillator are coupled to one output terminal for the converter and the return nodes from the lower oscillator are coupled to another output terminal for the converter such that the input voltage is upconverted to an output voltage measured across the pair of output terminals.

16. The self-oscillating DC-DC converter of claim 9 wherein the supply nodes from the upper oscillator are coupled to one input terminal for the converter and the return node from the lower oscillator are coupled to another input terminal for the converter such that the pair of input terminals are configured to receive an input voltage; and the supply nodes from the lower oscillator are coupled to one output terminal for the lower oscillator and the return nodes from the lower ring oscillator are coupled to another output terminal for the lower oscillator such the input voltage is downconverted to an output vol

Assignees

• Univ Michigan Regents

Inventors

• Jung Wanyeong
• Oh Sechang
• Bang Suyoung
• Lee Yoonmyung
• Sylvester Dennis
• Blaauw David T

Classifications

• H02M1/36

  Means for starting or stopping converters · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title