Behavioral design recovery from flattened netlist

Patent metadata

Field	Value
Publication number	US-11010519-B2
Application number	US-202016897642-A
Country	US
Kind code	B2
Filing date	Jun 10, 2020
Priority date	Jun 10, 2019
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

First claim

The invention claimed is:

1. A non-transitory storage medium storing instructions which are readable and executable by an electronic processor to perform a Register Transfer Level (RTL) representation recovery method, the instructions including:
instructions readable and executable by the electronic processor to convert a netlist representing an integrated circuit (IC) design to a graph comprising nodes belonging to a set of node types and edges connecting the nodes, wherein the set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components;
instructions readable and executable by the electronic processor to convert the graph to a standardized graph by replacing subgraphs of the graph with standardized subgraphs; and
instructions readable and executable by the electronic processor to generate an RTL representation of the standardized graph by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

2. The non-transitory storage medium of claim 1 , wherein the wire node type has a single input signal and one or more output signals, wherein the value of each output signal is equal to the value of the single input signal.

3. The non-transitory storage medium of claim 2 , wherein the instance node type has one or more input signals and a single output signal.

4. The non-transitory storage medium of claim 3 , wherein the set of node types further includes an input node type representing an input terminal of the netlist, an output node type representing an output terminal of the netlist, and a constant node type representing a constant signal source.

5. The non-transitory storage medium of claim 1 , wherein the instructions readable and executable by the electronic processor to replace subgraphs of the graph with standardized subgraphs include:
instructions readable and executable by the electronic processor to replace nodes of the graph with standardized nodes using an IC nomenclature database; and
instructions readable and executable by the electronic processor to replace a subgraph that includes a look-up table (LUT) node with a standardized subgraph that does not include a LUT node.

6. The non-transitory storage medium of claim 5 , wherein the subgraph that includes the LUT node is replaced by generating a truth table for the LUT node, converting the truth table to a Boolean expression, and generating the standardized subgraph that does not include a LUT node to represent the Boolean expression.

7. The non-transitory storage medium of claim 1 , wherein the instructions readable and executable by the electronic processor to convert the netlist representing the IC design to the graph include instructions readable and executable by the electronic processor to parse the netlist to create an abstract syntax tree (AST).

8. The non-transitory storage medium of claim 1 , wherein the RTL representation of the standardized graph is generated by operations further including:
building synchronous device declarations in the HDL for synchronous device subgraphs of the standardized graph using a template RTL library, and
instantiating instances of the declared synchronous devices in the HDL corresponding to the synchronous device subgraphs of the standardized graph.

9. A device for recovering a Register Transfer Level (RTL) representation from a netlist representing an integrated circuit (IC) design, the device comprising:
an electronic processor; and
a non-transitory storage medium storing instructions readable and executable by the electronic processor to perform an RTL representation recovery method, the instructions including:
instructions readable and executable by the electronic processor to convert a netlist representing an IC design to a graph comprising nodes belonging to a set of node types and edges connecting the nodes, wherein the set of node types includes an instance node type representing an electronic component and a wire node type having a single input signal and one or more output signals with the value of each output signal being equal to the value of the single input signal;
instructions readable and executable by the electronic processor to convert the graph to a standardized graph by replacing subgraphs of the graph with standardized subgraphs; and
instructions readable and executable by the electronic processor to generate an RTL representation of the standardized graph.

10. The device of claim 9 , wherein the RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

11. The device of claim 10 , wherein the RTL representation of the standardized graph is generated by operations further including:
building synchronous device declarations in the HDL for synchronous device subgraphs of the standardized graph using a template RTL library, and
instantiating instances of the declared synchronous devices in the HDL corresponding to the synchronous device subgraphs of the standardized graph.

12. The device of claim 9 , wherein the instance node type has one or more input signals and a single output signal, and the set of node types further includes an input node type representing an input terminal of the netlist, an output node type representing an output terminal of the netlist, and a constant node type representing a constant signal source.

13. The device of claim 9 , wherein the instructions readable and executable by the electronic processor to replace subgraphs of the graph with standardized subgraphs include:
instructions readable and executable by the electronic processor to replace nodes of the graph with standardized nodes using an IC nomenclature database; and
instructions readable and executable by the electronic processor to replace a subgraph that includes a look-up table (LUT) node with a standardized subgraph that does not include a LUT node.

14. The device of claim 13 , wherein the subgraph that includes the LUT node is replaced by generating a truth table for the LUT node, converting the truth table to a Boolean expression, and generating the standardized subgraph that does not include a LUT node to represent the Boolean expression.

15. The device of claim 9 , wherein the instructions readable and executable by the electronic processor to convert the netlist representing the IC design to the graph include instructions readable and executable by the electronic processor to parse the netlist to create an abstract syntax tree (AST).

16. A Register Transfer Level (RTL) representation recovery method comprising:
converting a netlist representing an integrated circuit (IC) design to a graph comprising nodes belonging to a set of node types and edges connecting the nodes, wherein the set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components;
converting the graph to a standardized graph by replacing subgraphs of the graph with standardized subgraphs; and
generating an RTL representation of the standardized graph by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from in

Assignees

• Battelle Memorial Institute

Inventors

• Kimura Adam G
• Elliott Andrew S
• Perkins Daniel A

Classifications

• H01J2237/31798

  detecting pattern defects · CPC title

• G06F30/323 Primary

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2117/06

  Spare resources, e.g. for permanent fault suppression · CPC title

• G06F2115/06

  Structured ASICs · CPC title