Model level power consumption optimization in hardware description generation

Patent metadata

Field	Value
Publication number	US-9355000-B1
Application number	US-201113216024-A
Country	US
Kind code	B1
Filing date	Aug 23, 2011
Priority date	Aug 23, 2011
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A system and method evaluates power information for a high-level model to be implemented in target hardware, and performs one or more power-reducing transmutations on the model. Transmutations may include moving one or more components from a fast rate region to a slow rate region, reducing bit width of data, signals, or other values, and replacing multiple instances of a resource with a shared instance of the resource. An in-memory representation of the model may be generated that reduces the model to a plurality of core components. A power score evaluation engine may assign power scores to the core components. Power scores may be retrieved from one or more power score database. The power scores may be non-dimensional scores representing power consumption relationships among the core components, and be target independent. Hints or alerts regarding suggested changes to the model to optimize power consumption may be presented to a user. A revised model incorporating the suggested changes may be constructed. The one or more transmutations resulting in a lowest total power score may be selected for hardware generation.

First claim

What is claimed is:

1. A method comprising:
accessing a graphical model having executable semantics,
the graphical model created in a graphical modeling environment that defines
core components that represent base level operations of the graphical modeling environment and, when executed by the graphical modeling environment, perform base level operations, and
high-level graphical blocks that represent high-level functions of the graphical modeling environment relative to the core components and, when executed by the graphical modeling environment perform the high-level functions, the high-level graphical blocks formed from combinations of the core components,

the graphical model including a first set of the core components defined within the graphical modeling environment, and
the graphical model having a functional behavior;

accessing power scores assigned to the core components defined within the graphical modeling environment;
computing, by a processor, a total power score for the graphical model, the total power score
being a function of the power scores assigned to the first set of the core components included in the graphical model, and
determined without translation of the graphical model into a low-level hardware design form;

automatically performing at least one transmutation to the graphical model, the at least one transmutation automatically creating a modified graphical model, the modified graphical model
having a functional behavior equivalent to the functional behavior of the graphical model, and
including a second set of the core components defined within the graphical modeling environment;

computing, by the processor, a total power score for the modified graphical model, the total power score for the modified graphical model being a function of the power scores assigned to the second set of the core components included in the modified graphical model, the total power score for the modified graphical model being less than the total power score computed for the graphical model; and
performing at least one of
presenting a visual representation of the modified graphical model on an output device, or
generating a hardware description for the modified graphical model.

2. The method of claim 1 wherein
the graphical model includes first and second regions, the second region operating at a higher rate than the first region, and
the at least one transmutation modifies the graphical model by moving one or more of the particular core components from the second region to the first region.

3. The method of claim 1 wherein the power scores assigned to the core components are:
represented using non-dimensional values, and
independent of target hardware.

4. The method of claim 1 further comprising:
automatically performing a plurality of transmutations to the graphical model;
computing a total power score for each of the plurality of transmutations performed on the graphical model;
comparing the computed total power scores; and
selecting the transmutation from the plurality of transmutations that produces the lowest computed total power score.

5. The method of claim 4 further comprising:
presenting the selected transmutation to a user.

6. The method of claim 5 where the selected transmutation is presented through a revised version of the graphical model.

7. The method of claim 1 further comprising:
providing a plurality of data structures, each data structure storing a set of power scores for the core components;
receiving a selection of a given data structure; and
utilizing the set of power scores stored in the given data structure in computing the total power score for the graphical model.

8. The method of claim 1 wherein the total power score computed for the graphical model is non-denominational.

9. The method of claim 1 wherein the low-level hardware design form is a Register Transfer Level (RTL) form.

10. The method of claim 1 further comprising:
storing the total power score computed for the graphical model in a memory.

11. A method comprising:
constructing a graphical model having executable semantics in a graphical modeling environment that defines
core components that represent base level operations of the graphical modeling environment and, when executed by the graphical modeling environment, perform the base level operations, and
high-level graphical blocks that represent high-level functions of the graphical modeling environment relative to the core components and, when executed by the graphical modeling environment perform the high-level functions, the high-level graphical blocks formed from combinations of the core components, the graphical model
having a behavior, and
including a first set of the core components defined within the graphical modeling environment;

accessing power scores assigned to the core components defined within the graphical modeling environment;
computing, by a processor, a total power score for the graphical model, the total power score
being a function of the assigned power scores for the first set of the core components included in the graphical model, and
determined without translation of the graphical model into a low-level hardware design form;

automatically updating the total power score while the graphical model is being constructed in the graphical modeling environment;
performing at least one transmutation to the graphical model, the at least one transmutation creating a modified graphical model that preserves the behavior of the graphical model, the modified graphical model having a second set of the core components;
computing, by the processor, a total power score for the modified graphical model, the total power score for the modified graphical model being a function of the power scores assigned to the second set of the core components, the total power score for the modified graphical model being less than the total power score computed for the graphical model; and
displaying the total power score computed for the modified graphical model.

12. The method of claim 11 further comprising:
presenting the modified graphical model on a display.

13. The method of claim 11 further comprising:
generating a hardware description from the modified graphical model.

14. The method of claim 11 wherein the low-level hardware design form is a Register Transfer Level (RTL) form.

15. A non-transitory computer readable medium comprising program instructions, the program instructions when executed by one or more processors operable to:
receive a graphical model having executable semantics, the graphical model adapted to make use of:
core components that represent base level operations and, when executed, perform the base level operations, and
high-level graphical blocks that represent high-level functions relative to the core components and, when executed, perform the high-level functions, the high-level graphical blocks formed from combinations of the core components, the graphical model
including a first set of the core components, and
having a functional behavior;

access power scores assigned to the core components;
compute a total power score for the graphical model, the total power score
being a function of the power scores assigned to the first set of the core components included in the graphical model, and
determined without translation of the graphical model into a low-level hardware design form;

perform automatically at least one transmutation on the graphical model, the at least one transmutation automatically creating a modified graphical model having a functional behavio

Assignees

• Biswas Partha
• Zhao Zhihong
• Chen Wang
• Gu Yongfeng
• Mathworks Inc

Inventors

• Biswas Partha
• Zhao Zhihong
• Chen Wang
• Gu Yongfeng

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F11/3062 Primary

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G06F2217/78

  Physics · mapped topic