Methods and Systems for Scalable and Distributed Address Mapping Using Non-Volatile Memory Modules

Patent metadata

Field	Value
Publication number	US-2016019160-A1
Application number	US-201514597167-A
Country	US
Kind code	A1
Filing date	Jan 14, 2015
Priority date	Jul 17, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

In a method to provide scalable and distributed address mapping in a storage device, a host command that specifies an operation to be performed and a logical address corresponding to a portion of memory within the storage device is received or accessed. A storage controller of the storage device maps the specified logical address to a first subset of a physical address, using a first address translation table, and identifies an NVM module of the plurality of NVM modules, in accordance with the first subset of a physical address. The method further includes, at the identified NVM module, mapping the specified logical address to a second subset of the physical address, using a second address translation table, identifying the portion of non-volatile memory within the identified NVM module corresponding to the specified logical address, and executing the specified operation on the portion of memory in the identified NVM module.

First claim

What is claimed is:

1 . A method for operating a storage device having a plurality of NVM modules, each NVM module including two or more non-volatile memory devices, the method comprising:
receiving or accessing a host command that specifies an operation to be performed and a logical address corresponding to a portion of non-volatile memory within the storage device; at a storage controller for the storage device:
mapping the specified logical address to a first subset of a physical address corresponding to the specified logical address, using a first address translation table;
identifying an NVM module of the plurality of NVM modules, in accordance with the first subset of the physical address;
at the identified NVM module:
mapping the specified logical address to a second subset of the physical address corresponding to the specified logical address, using a second address translation table;
identifying the portion of non-volatile memory within the identified NVM module corresponding to the second subset of the physical address; and
executing the specified operation on the identified portion of non-volatile memory in the identified NVM module.

2 . The method of claim 1 , wherein, when the host command requests a write operation or an erase operation, the method further comprises:
at the identified NVM module:
updating the second address translation table in accordance with the requested operation.

3 . The method of claim 1 , wherein the host command requests a write operation or an erase operation, and the method further comprises:
at the storage controller for the storage device:
updating the first address translation table in accordance with the requested operation.

4 . The method of claim 1 , wherein, when the host command is a read command, executing the specified operation on the identified portion of non-volatile memory in the identified NVM module comprises reading data from the identified portion of non-volatile memory in the identified NVM module.

5 . The method of claim 1 , wherein the second address table is stored in non-volatile memory in the identified NVM module.

6 . The method of claim 5 , wherein the second address table is stored in non-volatile memory in the identified NVM module using a single-layer cell (SLC) mode of operation.

7 . The method of claim 1 , wherein the first subset of the physical address comprises a predefined number of most significant bits of the physical address and the second subset of the physical address comprises a predefined number of least significant bits of the physical address.

8 . The method of claim 1 , wherein the second address table is pre-loaded into cache memory in the identified NVM module.

9 . The method of claim 1 , wherein, the host command requests a write operation, and the method further comprises:
at the storage controller for the storage device:
determining and storing a write count associated with the first subset of the physical address.

10 . The method of claim 1 , wherein the method further comprises, at the identified NVM module:
conveying to the storage controller metadata corresponding to the identified portion of non-volatile memory in the identified NVM module corresponding to the specified logical address.

11 . The method of claim 1 , wherein the storage device comprises one or more flash memory devices.

12 . A storage device, comprising:
an interface for coupling the storage device to a host system; a plurality of NVM modules, each NVM module including two or more non-volatile memory devices; a storage controller having one or more processors, the storage controller configured to:
receive or access a host command specifying an operation to be performed and a logical address corresponding to a portion of non-volatile memory within the storage device;
map the specified logical address to a first subset of a physical address corresponding to the specified logical address, using a first address translation table; and
identify an NVM module of the plurality of NVM modules, in accordance with the first subset of the physical address; and
wherein the identified NVM module of the plurality of NVM modules is configured to:
map the specified logical address to a second subset of the physical address corresponding to the specified logical address, using a second address translation table;
identify the portion of non-volatile memory within the NVM module corresponding to the second subset of the physical address; and
execute the specified operation on the identified portion of non-volatile memory in the identified NVM module.

13 . The storage device of claim 12 , wherein the host command requests a write operation or an erase operation, and the NVM module is further configured to:
update the second address translation table in accordance with the requested operation.

14 . The storage device of claim 12 , wherein the host command requests a write operation or an erase operation, and the storage controller is further configured to:
update the first address translation table in accordance with the requested operation.

15 . The storage device of claim 12 , wherein the second address table is stored in non-volatile memory in the identified NVM module.

16 . The storage device of claim 15 , wherein the second address table is stored in non-volatile memory in the identified NVM module using a single-layer cell (SLC) mode of operation.

17 . The storage device of claim 12 , wherein the first subset of the physical address comprises a predefined number of most significant bits of the physical address and the second subset of the physical address comprises a predefined number of least significant bits of the physical address.

18 . The storage device of claim 12 , wherein the second address table is pre-loaded into cache memory in the identified NVM module.

19 . The storage device of claim 12 , wherein the host command requests a write operation, and the storage controller is further configured to:
determine and store a write count associated with the first subset of a physical address in accordance with the requested operation.

20 . The storage device of claim 12 , wherein the identified NVM module is further configured to:
convey to the storage controller, metadata corresponding to the identified portion of non-volatile memory in the identified NVM module corresponding to the specified logical address.

21 . The storage device of claim 12 , wherein the storage device comprises one or more flash memory devices.

22 . A storage device, comprising:
an interface for coupling the storage device to a host system; a plurality of NVM modules, each NVM module including two or more non-volatile memory devices; a storage controller having one or more processors, the storage controller including:
a command module to receive or access a host command specifying an operation to be performed and a logical address corresponding to a portion of non-volatile memory within the storage device;
a map module to map the specified logical address to a first subset of a physical address corresponding to the specified logical address, using a first address translation table; and
a forwarding module to forward a command, corresponding to the host command, to an NVM module of the plurality of NVM modules identified in accordance with the first subset of the physical address; and
wherein the identified NVM module of the plurality of NVM modules include

Assignees

• Sandisk Entpr Ip Llc

Inventors

• Mohan Vidyabhushan
• Frayer Jack Edward

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/202

  Non-volatile memory · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F2212/1041

  Resource optimization · CPC title