Test architecture with an FPGA based test board to simulate a DUT or end-point

Patent metadata

Field	Value
Publication number	US-11009550-B2
Application number	US-201815914553-A
Country	US
Kind code	B2
Filing date	Mar 7, 2018
Priority date	Feb 21, 2013
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

First claim

What is claimed is:

1. An automated test equipment (ATE) system comprising:
a first test board comprising a first FPGA and a processor, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a device under test (DUT), wherein the processor is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between the processor and the first FPGA in a different manner; and
a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for the DUT, wherein the second FPGA is further programmed to simulate the DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

2. The system of claim 1 , wherein the processor is operable to generate commands for coordinating a test sequence between the first FPGA and the second FPGA.

3. The system of claim 1 , wherein the first core is programmed with a PCIe protocol.

4. The system of claim 1 , wherein the second core is programmed to implement a protocol for a PCIe 4.0 solid state device (SSD) DUT.

5. The system of claim 1 , wherein the second core is programmed to implement a protocol for a SATA DUT.

6. The system of claim 1 , wherein the first test board and second test board have analogous hardware and layout designs.

7. The system of claim 1 , wherein the first test board connects with the interface board via a PCIe connector.

8. The system of claim 1 , wherein the second FPGA comprises an algorithmic pattern generator configured to automatically generate patterns in accordance with the communication protocol programmed into the second core.

9. The system of claim 1 , wherein the second FPGA is communicatively coupled with a memory module on the second test board, and wherein a test pattern for testing the communication link is stored on the memory module.

10. An automated test equipment (ATE) system comprising:
a first test board comprising a first FPGA and a controller, wherein the first FPGA comprises two cores, wherein each core is programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a device under test (DUT) of a prescribed type, wherein the controller is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between the controller and the first FPGA in a different manner;
a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a DUT of the prescribed type, wherein the second FPGA is further programmed to simulate a DUT of the prescribed type; and
a third test board comprising a third FPGA communicatively coupled to the first test board, wherein the third FPGA comprises a third core programmed to implement a communication protocol for a DUT of the prescribed type, and wherein the third FPGA is further programmed to simulate a DUT of the prescribed type.

11. The system of claim 10 , wherein the two cores configured on the first FPGA are programmed with an analogous protocol, and wherein the second core and the third core are programmed to implement a protocol for a DUT that matches a protocol programmed on the two cores.

12. The system of claim 11 , wherein the two cores are programmed with a PCIe protocol, and wherein the second core and third core are programmed to implement a SSD PCIe 4.0 DUT protocol.

13. The system of claim 10 , wherein the two cores configured on the first FPGA are programmed with different protocols, and wherein the second core and the third core are programmed to implement a protocol for a device under test that matches a respective core on the first FPGA.

14. The system of claim 10 , wherein a first one of the two cores in configured with a PCIe protocol and a second one of the two cores is configured with a SATA protocol, and wherein the second core is communicatively coupled to the first one of the two cores and programmed to implement a SSD PCIe 4.0 protocol and the third core is communicatively coupled to the second one of the two cores and programmed to implement a SATA SSD DUT protocol.

15. The system of claim 10 , wherein the second FPGA and the third FPGA each comprise an algorithmic pattern generator configured to generate patterns in accordance with a communication protocol programmed into a respective core.

16. A method for testing using an automated test equipment (ATE) comprising:
communicatively coupling a controller and a first FPGA using a first test board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a device under test (DUT) of a prescribed type, wherein the controller is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to differently allocate functionality for generating commands and for generating data between the controller and the first FPGA; and
communicatively coupling a second test board comprising a second FPGA to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a DUT of the prescribed type, wherein the second FPGA is further programmed to simulate a DUT of the prescribed type, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

17. The system of claim 16 , wherein the controller is operable to generate commands for coordinating a test sequence between the first FPGA and the second FPGA.

18. The system of claim 16 , wherein the second core is programmed to implement a protocol for a PCIe 4.0 solid state device (SSD) DUT.

19. The system of claim 16 , wherein the first test board and second test board have analogous hardware and layout designs.

20. The system of claim 16 , wherein the second FPGA comprises an algorithmic pattern generator configured to automatically generate patterns in accordance with the communication protocol programmed into the second core.

Assignees

• Advantest Corp

Inventors

• Champoux Duane
• Su Mei-Mei

Classifications

• G01R31/31907 Primary

  Modular tester, e.g. controlling and coordinating instruments in a bus based architecture · CPC title

• G01R31/31908

  Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns · CPC title

• G01R31/31919

  Storing and outputting test patterns (G01R31/31924 takes precedence; arithmetic and random test patterns generator) · CPC title

• G01R31/2601

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

• G01R31/31903

  tester configuration · CPC title