Tester with mixed protocol engine in a FPGA block

Patent metadata

Field	Value
Publication number	US-9952276-B2
Application number	US-201313773580-A
Country	US
Kind code	B2
Filing date	Feb 21, 2013
Priority date	Feb 21, 2013
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test.

First claim

What is claimed is:

1. An automated test equipment (ATE) apparatus comprising:
a system controller communicatively coupled to a tester processor, wherein said system controller is operable to transmit instructions for performing an automated test to said tester processor;
a plurality of Field Programmable Gate Arrays (FPGA) components coupled to said tester processor, wherein each of said plurality of FPGA components is programmed to comprise at least one reconfigurable circuit for implementing one of a plurality of communication protocols, wherein a communication protocol is operable to be programmed on an associated FPGA, and wherein each of said plurality of FPGA components is operable to access a bit-stream to program an associated at least one reconfigurable circuit from a memory on said system controller with said one of a plurality of communication protocols, wherein said tester processor is configured to determine one of a plurality of hardware acceleration modes for executing tests on a plurality of devices under test (DUTs) in accordance with instructions received from said system controller, wherein each of said hardware acceleration modes is configured to distribute functionality for generating commands and for generating data to test the plurality of DUTs between said tester processor and said plurality of FPGA components, wherein each hardware acceleration mode allocates command generation and data generation responsibility between the tester processor and the plurality of FPGA components in a different manner; and
at least one communication port for communicating with a device under test (DUT), wherein said plurality of FPGA components is operable to write test data to said a plurality of DUTs and operable to read test data from said plurality of DUTs in accordance with said instructions from said system controller using one of said plurality of communication protocols.

2. The apparatus of claim 1 wherein said system controller and said tester processor are programmed within said FPGA.

3. The apparatus of claim 1 wherein one of said system controller and said tester processor are programmed within said FPGA.

4. The apparatus of claim 1 wherein at least one of the plurality of communication protocols is selected from the group comprising: Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), and Serial AT Attachment (SATA).

5. The apparatus of claim 1 further comprising a user interface operable to allow user selection of a protocol to be programmed on said at least one reconfigurable circuit.

6. The apparatus of claim 1 wherein said plurality of devices to be tested (DUTs) are operable to be mounted on a test load board, and further wherein said plurality of FPGA components communicate with said DUTs through said test load board.

7. The apparatus of claim 1 wherein said plurality of FPGA components comprise a first set that is programmed to comprise a first communication protocol and a second set that is programmed to comprise a second communication protocol.

8. The apparatus of claim 1 wherein at least one of said plurality of FPGA components comprise a first set of reconfigurable circuits that is operable to implement a first communication protocol and a second set of reconfigurable circuits that is operable to implement a second communication protocol.

9. The apparatus of claim 1 wherein at least one of said plurality of DUTs comprises at least two circuits for communicating in communication protocols, wherein each of said at least two circuits implement a different protocol.

10. The apparatus of claim 9 wherein said at least two circuits are operable to operate simultaneously.

11. A method for testing using an automated test equipment (ATE), said method comprising:
transmitting instructions for performing an automated test from a system controller to a tester processor;
programming at least one reconfigurable circuit for implementing one of a plurality of communication protocols onto each of a plurality of Field Programmable Gate Arrays (FPGA) components coupled to said tester processor, wherein a communication protocol is operable to be programmed on an associate FPGA and wherein each of said plurality of FPGA components is operable to access a bit-stream to program an associated at least one reconfigurable circuit from a memory on said system controller with said one of a plurality of communication protocols;
writing test data to a plurality of devices to be tested (DUTs) from said plurality of FPGA components using said one of a plurality of communication protocols;
reading test data from said plurality of DUTs to said plurality of FPGA components using said one of a plurality of communication protocols, wherein both said writing and said reading is conducted in accordance with said instructions from said system controller, wherein said tester processor is configured to determine one of a plurality of hardware acceleration modes for executing tests on said plurality of DUTs, wherein each of said hardware acceleration modes is configured to distribute functionality for generating commands and for generating data between said tester processor and said plurality of FPGA components in order to test said plurality of DUTs, wherein each hardware acceleration mode allocates command generation and data generation responsibility between the tester processor and the plurality of FPGA components in a different manner.

12. The method of claim 11 wherein at least one of the plurality of communication protocols is selected from the group comprising: Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), and Serial AT Attachment (SATA).

13. The method of claim 11 further comprising selecting a communication protocol to be programmed on said at least one reconfigurable circuit based on a user selection from a user interface coupled to said system controller.

14. The method of claim 11 further comprising mounting said plurality of devices to be tested (DUTs) on a test load board, wherein said plurality of FPGA components communicate with said DUTs through said test load board.

15. The method of claim 11 further comprising programming a first set of said plurality of FPGA components to comprise a first communication protocol and programming a second set of said plurality of FPGA components to comprise a second communication protocol.

16. The method of claim 11 further comprising programming at least one of said plurality of FPGA components to comprise a first set of reconfigurable circuits that is operable to implement a first communication protocol and a second set of reconfigurable circuits that is operable to implement a second communication protocol.

17. The method of claim 11 further comprising communicating with at least one DUT from said plurality of DUTs using a first communication protocol and a second communication protocol, wherein said at least one DUT comprises at least two reconfigurable circuits for implementing communication protocols.

18. The method of claim 17 further comprising testing said at least two reconfigurable circuits simultaneously.

19. A tester system comprising:
a system controller for controlling a test program and coupled to a bus;
a plurality of modules coupled to said bus and each operable to test a plurality of devices under test (DUTs) wherein each module comprises:
a tester processor coupled to said bus;
a plurality of configurable blocks communicatively coupled to said tester processo

Assignees

• Advantest Corp

Inventors

• Frediani Jonh
• Niemic Andrew

Classifications

• G01R31/2834 Primary

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/318307

  computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging · CPC title