Test apparatus based on binary vector

Patent metadata

Field	Value
Publication number	US-10163525-B2
Application number	US-201715456195-A
Country	US
Kind code	B2
Filing date	Mar 10, 2017
Priority date	May 17, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT.

First claim

What is claimed is:

1. A test apparatus comprising:
a device under test (DUT) configured to exchange data using a serial interface protocol; and
a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT,
wherein the test controller further comprises a DC offset block configured to transmit the binary vector to the DUT through at least one differential signal line pair and to adjust a DC offset in the at least one differential signal line pair.

2. The test apparatus as set forth in claim 1 , wherein the test controller comprises:
a buffer configured to store the binary vector; and
a serializer configured to convert the binary vector that was stored into a serial signal corresponding to the serial interface protocol.

3. The test apparatus as set forth in claim 2 , wherein the serializer is further configured to convert the binary vector into a differential signal corresponding to the serial interface protocol and accelerates and output data.

4. The test apparatus as set forth in claim 1 , wherein the binary vector is a sequence of a binary signal received via a differential signal in the physical layer of the serial interface protocol.

5. The test apparatus as set forth in claim 1 , wherein the DC offset block comprises at least one passive element configured to apply the DC offset to the differential signal line in response to a DC offset control signal provided from the test controller.

6. A general-purpose test apparatus comprising:
a test controller configured to translate received binary data into a serial transmission signal;
a device under test (DUT) configured to receive the serial transmission signal from the test controller via a differential signal line pair; and
a DC offset block configured to adjust a DC offset of the differential signal line pair in response to a DC offset control signal from the test controller,
wherein the DC offset block comprises at least one passive element.

7. The general-purpose test apparatus as set forth in claim 6 , wherein the test controller is further configured to generate the DC offset control signal based on a type of an interface protocol of the DUT.

8. The general-purpose test apparatus as set forth in claim 6 , wherein the test controller is further configured to determine a level of the DC offset control signal based on an operation mode of the DUT.

9. The general-purpose test apparatus as set forth in claim 6 , wherein the DC offset block comprises an inductor configured to receive the DC offset control signal and to provide the DC offset control signal as a DC offset of at least one line among the differential signal line pair.

10. The general-purpose test apparatus as set forth in claim 6 , wherein the DC offset block comprises a plurality of divided resistors configured to divide the DC offset control signal and provide the divided DC offset control signal as a DC offset of at least one line among the differential signal line pair.

11. A test apparatus, comprising:
a test controller that is configured to communicate with a device under test (DUT) using a multi-layer test protocol; and
an automated test equipment unit that is coupled to the test controller;
wherein the automated test equipment unit is configured to implement at least one layer of the multi-layer test protocol and the test controller is configured to implement remaining layers of the multi-layer test protocol other than the at least one layer of the multi-layer test protocol implemented by the automated test equipment;
wherein the automated test equipment unit is further configured to translate a command for a device under test into a binary vector that corresponds to a physical layer of the multi-layer test protocol; and
wherein the physical layer of the multi-layer test protocol is defined by an M-PHY specification.

12. The test apparatus of claim 11 ,
wherein the test controller comprises:
a buffer configured to store the binary vector received from the automated test equipment unit; and
a serializer configured to convert the binary vector into a serial signal corresponding to a serial interface protocol for communication to the DUT.

13. The test apparatus of claim 12 , wherein the serializer is configured to accelerate a data rate of the serial signal to match a transmission rate of a link between the test controller and the DUT.

14. The test apparatus of claim 11 , wherein the at least one layer of the multi-layer test protocol comprises at least one of a link layer of the multi-layer test protocol and a transaction layer of the multi-layer test protocol.

15. The test apparatus of claim 11 , wherein the multi-layer test protocol is one of a Peripheral Component Interconnect Express (PCIe) protocol, a Universal Flash Storage (UFS) protocol, and a Next Generation Form Factor (M.2) protocol.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Joosung
• Shin Seongseob
• Lee Moon-Ho
• Choi Woonsup

Classifications

• G11C29/56016 Primary

  Apparatus features · CPC title

• H04B2001/305

  using DC offset compensation techniques · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G11C29/48 Primary

  Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths · CPC title

• G11C29/56012

  Timing aspects, clock generation, synchronisation · CPC title