Interconnect structure without barrier layer on bottom surface of via
US-2019006230-A1 · Jan 3, 2019 · US
Integrated circuit having a single damascene wiring network
US11004736B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11004736-B2 |
| Application number | US-201916516775-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 19, 2019 |
| Priority date | Jul 19, 2019 |
| Publication date | May 11, 2021 |
| Grant date | May 11, 2021 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method for fabricating a multi-layered wafer includes depositing a metal liner following by a seed layer including a metal in a trench arranged in an inter-metal dielectric (IMD). An end of the trench contacts a metal via of an interconnect structure. Heat is applied to drive the metal of the seed layer into the IMD and form a barrier layer along a sidewall of the trench.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a wafer, the method comprising: depositing a metal liner followed by a seed layer in a trench arranged in an inter-metal dielectric (IMD), an end of the trench contacting a metal via of an interconnect structure, and the seed layer comprising a metal; and applying heat to drive the metal of the seed layer into the IMD and form a barrier layer along sidewalls of the trench and at least partially along sidewalls of the metal via. 2. The method of claim 1 , wherein the seed layer comprises manganese, copper, or a combination thereof. 3. The method of claim 1 further comprising depositing another metal to fill the trench. 4. The method of claim 3 , wherein the another metal comprises copper, tungsten, aluminum, cobalt, ruthenium, rhodium, platinum, or any combination thereof. 5. The method of claim 1 , wherein the barrier layer comprises a compound that results from reaction of the metal in the seed layer and a compound of the IMD. 6. The method of claim 1 , wherein the seed layer is manganese. 7. The method of claim 1 , wherein the seed layer comprises copper and manganese. 8. A method of fabricating a wafer, the method comprising: depositing a metal liner following by a seed layer in a trench arranged in an inter-metal dielectric (IMD), an end of the trench contacting a metal via of an interconnect structure, the metal via comprising a metal fill, the seed layer comprising a first metal and a second metal; and applying heat to drive the first metal into the IMD and form a barrier layer along a sidewall of the trench and at least partially along sidewalls of the metal via, the second metal remaining in the seed layer. 9. The method of claim 8 , wherein the first metal of the seed layer comprises manganese. 10. The method of claim 9 , wherein the second metal of the seed layer comprises copper. 11. The method of claim 8 further comprising depositing another metal to fill the trench. 12. The method of claim 11 , wherein the another metal comprises copper, tungsten, aluminum, cobalt, ruthenium, rhodium, platinum, or any combination thereof. 13. The method of claim 8 , wherein the barrier layer comprises a compound that results from reaction of the first metal and a compound of the IMD. 14. The method of claim 8 , wherein the barrier layer comprises MnSiO 3 .
Assignees
Inventors
Classifications
by diffusing metallic dopants to react with dielectrics · CPC title
based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title
Cross-sectional shapes or dispositions of interconnections · CPC title
using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title
in via holes or trenches · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US11004736B2 cover?
- A method for fabricating a multi-layered wafer includes depositing a metal liner following by a seed layer including a metal in a trench arranged in an inter-metal dielectric (IMD). An end of the trench contacts a metal via of an interconnect structure. Heat is applied to drive the metal of the seed layer into the IMD and form a barrier layer along a sidewall of the trench.
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10W20/057. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 11 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).