Memory arrays, and methods of forming memory arrays

Patent metadata

Field	Value
Publication number	US-11004494-B2
Application number	US-201916267087-A
Country	US
Kind code	B2
Filing date	Feb 4, 2019
Priority date	Nov 6, 2017
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

First claim

We claim:

1. An assembly comprising:
an active material structure including a bit contact region and a cell contact region;
a first redistribution pad coupled with the bit contact region;
a second redistribution pad coupled with the cell contact region;
a bitline over the active material structure and electrically connected with the first redistribution pad;
a programmable device over the active material structure and electrically connected with the second redistribution pad; and
wherein the first redistribution pad is horizontally expanded relative to the bit contact region to allow the bitline to be horizontally offset relative to the bit contact region.

2. The assembly of claim 1 , wherein the programmable device comprises a capacitor.

3. The assembly of claim 1 , wherein the active material structure comprises monocrystalline silicon, and wherein each of the first and second redistribution pads comprises polycrystalline silicon.

4. The assembly of claim 1 , further comprising a conductive plug between the second redistribution pad and the programmable device, wherein the conductive plug is approximately vertically aligned with the cell contact region.

5. The assembly of claim 4 , wherein each of the bitline and the conductive plug comprises a metal.

6. The assembly of claim 4 , wherein an upper surface of the bitline is recessed downwardly relative to an upper surface of the conductive plug.

7. The assembly of claim 1 , wherein an upper surface of the bit contact region is vertically offset relative to an upper surface of the cell contact region.

8. The assembly of claim 7 , wherein the upper surface of the bit contact region is recessed downwardly relative to the upper surface of the cell contact region.

9. A memory array, comprising:
wordlines extending along a first direction;
bitlines extending along a second direction that crosses the first direction;
active material structures at regions where the wordlines and bitlines cross one another, each of the active material structures having a bit contact region and a cell contact region;
first redistribution pads coupled with the bit contact regions;
second redistribution pads coupled with the cell contact regions;
each of the bit contact regions being coupled with an associated one of the bitlines at least partially through one of the first redistribution pads; the first redistribution pads being horizontally expanded relative to the bit contact regions to allow the associated bitlines to be horizontally offset relative to the bit contact regions;
programmable devices coupled with the cell contact regions at least partially through the second redistribution pads;
the active material structures comprising a first material; and
the first and second redistribution pads comprising a second material which is different from the first material.

10. The memory array of claim 9 wherein the programmable devices are capacitors.

11. The memory array of claim 9 wherein the bit contact regions are vertically offset relative to the cell contact regions.

12. The memory array of claim 9 wherein the bit contact regions are not vertically offset relative to the cell contact regions.

13. The memory array of claim 9 wherein the first material comprises monocrystalline silicon, and wherein the second material comprise polycrystalline silicon.

14. The memory array of claim 9 wherein the first material of the active material structures is entirely covered by the second material of the first and second redistribution pads.

15. The memory array of claim 9 wherein the first material of the active material structures is not entirely covered by the second material of the first and second redistribution pads.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Wang Kuo-Chen
• Roberts Martin C
• Tran Diem Thy N
• Gomi Hideki
• Fishburn Fredrick D
• Pulugurtha Srinivas
• Koopmans Michel
• Hasunuma Eiji

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title