Memory arrays, and methods of forming memory arrays

Patent metadata

Field	Value
Publication number	US-10242726-B1
Application number	US-201816180542-A
Country	US
Kind code	B1
Filing date	Nov 5, 2018
Priority date	Nov 6, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

First claim

We claim:

1. An assembly comprising:
an active material structure including a bit contact region and a cell contact region;
a wordline buried in the active material structure, the wordline extending in a first direction between the bit contact region and the cell contact region;
a first redistribution pad coupled with the bit contact region;
a second redistribution pad coupled with the cell contact region;
a bitline extending in a second direction over the active material structure and being coupled with the first redistribution pad, the second direction crossing the first direction;
a programmable device over the active material structure and being coupled with the second redistribution pad; and
wherein the first redistribution pad is horizontally expanded to allow the bitline to be horizontally offset relative to the bit contact region.

2. The assembly of claim 1 , wherein the programmable device comprises a capacitor.

3. The assembly of claim 1 , wherein the active material structure comprises monocrystalline silicon, and wherein each of the first and second redistribution pads comprises polycrystalline silicon.

4. The assembly of claim 1 , further comprising a conductive plug between the second redistribution pad and the programmable device, wherein the conductive plug is approximately vertically aligned with the cell contact region.

5. The assembly of claim 4 , wherein each of the wordline, the bitline and the conductive plug comprises a metal.

6. The assembly of claim 4 , wherein an upper surface of the bitline is recessed downwardly relative to an upper surface of the conductive plug.

7. The assembly of claim 1 , wherein an upper surface of the bit contact region is vertically offset relative to an upper surface of the cell contact region.

8. The assembly of claim 7 , wherein the upper surface of the bit contact region is recessed downwardly relative to the upper surface of the cell contact region.

9. An assembly, comprising:
active material structures arranged in an array; the array having rows and columns; the rows extending along a first direction, and the columns extending along a second direction which crosses the first direction; each of the active material structures having a first side comprising a bit contact region, and a second side comprising a cell contact region;
first redistribution pads coupled with the bit contact regions;
second redistribution pads coupled with the cell contact regions;
bitlines coupled with the first redistribution pads;
programmable devices coupled with the second redistribution pads;
the first and second redistribution pads alternating with one another along the first direction;
the first redistribution pads being aligned along first columns extending in the second direction, with said first columns being exclusive to the first redistribution pads relative to the second redistribution pads; and
the second redistribution pads being aligned along second columns extending in the second direction, with said second columns being exclusive to the second redistribution pads relative to the first redistribution pads.

10. The assembly of claim 9 wherein the programmable devices are over the second redistribution pads.

11. The assembly of claim 9 wherein the programmable devices are capacitors.

12. The assembly of claim 9 wherein the active material structures comprise monocrystalline silicon, and wherein the first and second redistribution pads comprise polycrystalline silicon.

13. The assembly of claim 12 wherein the monocrystalline silicon of the active material structures is entirely covered by the polycrystalline silicon of the first and second redistribution pads.

14. The assembly of claim 12 wherein the monocrystalline silicon of the active material structures is not entirely covered by the polycrystalline silicon of the first and second redistribution pads.

15. A memory array, comprising:
wordlines extending along a first direction;
bitlines extending along a second direction that crosses the first direction;
active material structures at regions where the wordlines and bitlines cross one another, each of the active material structures having a first side comprising a bit contact region, and a second side comprising a cell contact region;
first redistribution pads coupled with the bit contact regions;
second redistribution pads coupled with the cell contact regions;
each of the bit contact regions being coupled with one of the bitlines at least partially through one of the first redistribution pads;
programmable devices proximate the cell contact regions; each of the cell contact regions being coupled with one of the programmable devices at least partially through one of the second redistribution pads;
the first and second redistribution pads alternating with one another along the first direction;
the active material structures comprising a first material; and
the first and second redistribution pads comprising a second material which is different from the first material.

16. The memory array of claim 15 wherein the programmable devices are capacitors.

17. The memory array of claim 15 wherein the bit contact regions are vertically offset relative to the cell contact regions.

18. The memory array of claim 15 wherein the bit contact regions are not vertically offset relative to the cell contact regions.

19. The memory array of claim 15 wherein the first material comprises monocrystalline silicon, and wherein the second material comprise polycrystalline silicon.

20. The memory array of claim 15 wherein the first material of the active material structures is entirely covered by the second material of the first and second redistribution pads.

21. The memory array of claim 15 wherein the first material of the active material structures is not entirely covered by the second material of the first and second redistribution pads.

22. The memory array of claim 15 wherein the first redistribution pads are aligned along first columns extending in the second direction, and wherein the second redistribution pads are aligned along second columns extending in the second direction.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Wang Kuo-Chen
• Roberts Martin C
• Tran Diem Thy N
• Gomi Hideki
• Fishburn Fredrick D
• Pulugurtha Srinivas
• Koopmans Michel
• Hasunuma Eiji

Classifications

• G11C11/4023 Primary

  using field effect transistors · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H01L27/10805

  Electricity · mapped topic

• H01L27/10847

  Electricity · mapped topic

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title