Method for implementing a line speed interconnect structure

Patent metadata

Field	Value
Publication number	US-11003459-B2
Application number	US-201916383212-A
Country	US
Kind code	B2
Filing date	Apr 12, 2019
Priority date	Mar 15, 2013
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.

First claim

What is claimed is:

1. A method for line speed cache access request processing, comprising:
receiving a plurality of cache access requests;
performing a pre-sorting of the plurality of cache access requests by a first stage to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory;
performing a combining of at least two cache access requests into a single cache access request where the at least two cache access requests are in adjacent positions after the pre-sorting in the first stage and splitting of a cache access request into at least two cache access requests, the at least two cache access requests and the single cache access request from the plurality of cache access requests, by a second stage; and
applying the plurality of cache access requests to the cache memory at line speed.

2. The method of claim 1 , wherein the first stage performs position shuffling, pairing, and splitting of the cache access requests based on cache address of each of the plurality of cache access requests.

3. The method of claim 1 , wherein the combining combines cache access requests that access a same position or address in the cache memory.

4. The method of claim 1 , wherein the splitting splits cache access requests that access requests to different positions or addresses in the cache memory.

5. The method of claim 1 , wherein the cache access requests presented to the second stage are virtual requests.

6. The method of claim 1 , wherein cache access requests to non-aligned addresses are split.

7. A processor device, comprising:
a cache memory; and
a cache controller coupled to the cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs a combining of at least two cache access requests into a single cache access request where the at least two cache access requests are in adjacent positions after the pre-sorting in the first stage and splitting of a cache access request into at least two cache access requests, the at least two cache access requests and the single cache access request from the plurality of cache access request by a second stage, and applies the plurality of cache access requests to the cache memory at line speed.

8. The processor of claim 7 , wherein the first stage performs position shuffling, pairing, and splitting of the cache access requests based on cache address of each of the plurality of cache access requests.

9. The processor of claim 7 , wherein the combining combines cache access requests that access a same position or address in the cache memory.

10. The processor of claim 7 , wherein the splitting splits cache access requests that access requests to different positions or addresses in the cache memory.

11. The processor of claim 7 , wherein the cache access requests presented to the second stage are virtual requests.

12. The processor of claim 7 , wherein cache access requests to non-aligned addresses are split.

13. A computer system, comprising:
a main memory;
a processor;
a cache memory coupled to the processor and the main memory; and
a cache controller coupled to the cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs a combining of at least two cache access requests into a single cache access request where the at least two cache access requests are in adjacent positions after the pre-sorting in the first stage and splitting of a cache access request into at least two cache access requests, the at least two cache access requests and the single cache access request from the plurality of cache access requests, by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.

14. The computer system of claim 13 , wherein the first stage of the cache controller performs position shuffling, pairing, and splitting of the cache access requests based on cache address of each of the plurality of cache access requests.

15. The computer system of claim 13 , wherein the combining combines cache access requests that access a same position or address in the cache memory.

16. The computer system of claim 15 , wherein the splitting splits cache access requests that access requests to different positions or addresses in the cache memory.

17. The computer system of claim 15 , wherein the cache access requests presented to the second stage are virtual requests.

18. The computer system of claim 15 , wherein cache access requests to non-aligned addresses are split.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F13/00 Primary

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G06F2212/1041

  Resource optimization · CPC title

• G06F15/17318

  Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all · CPC title

• G06F9/462

  with multiple register sets · CPC title

• G06F12/0886

  Variable-length word access · CPC title