Method for a stage optimized high speed adder

Patent metadata

Field	Value
Publication number	US-9753691-B2
Application number	US-201414214049-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 15, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.

First claim

What is claimed is:

1. A method for fast parallel adder processing, the method comprising:
receiving parallel inputs from a communications path, wherein each input comprises one bit;
adding the parallel inputs using a parallel structure, wherein the parallel structure is configured to accelerate the adding by utilizing a characteristic that the parallel inputs are one bit each, wherein the parallel structure comprises a first stage and a second stage, wherein the first stage comprises a four to one adder, wherein four one bit inputs are summed to produce one output comprising a three bit non-redundant result; and
transmitting resulting outputs from the adding to a subsequent stage.

2. The method of claim 1 , wherein the one bit parallel inputs comprise valid bits inside a hardware decoder.

3. The method of claim 1 , wherein the one bit parallel inputs comprise valid bits inside a hardware allocator.

4. The method of claim 1 , wherein the one parallel bit inputs comprise ready bits inside a hardware dispatch logic structure.

5. The method of claim 1 , wherein the one parallel bit inputs comprise retirement bits inside a hardware retirement logic structure.

6. The method of claim 1 , wherein the first stage further comprises a mix of four to one and two to one adders, and wherein inputs that are not fed through the first stage are fed into subsequent stages optimize the parallel adder circuit using the propagation delay differences of the subsequent stages.

7. A fast parallel adder circuit, the circuit comprising:
a parallel structure for receiving parallel inputs from a communications path, wherein each input comprises one bit, wherein the parallel structure comprises a first stage and a second stage, wherein the first stage comprises a four to one adder, wherein four one bit inputs are summed to produce one output comprising a three bit non-redundant result;
wherein the parallel structure adds the parallel inputs, and wherein the parallel structure is configured to accelerate addition by utilizing a characteristic that the parallel inputs are one bit each and to transmit resulting outputs of the addition to a subsequent stage.

8. The parallel adder circuit of claim 7 , wherein the one bit parallel inputs comprise valid bits inside a hardware decoder.

9. The parallel adder circuit of claim 7 , wherein the one bit parallel inputs comprise valid bits inside a hardware allocator.

10. The parallel adder circuit of claim 7 , wherein the one bit parallel inputs comprise ready bits inside a hardware dispatch logic structure.

11. The parallel adder circuit of claim 7 , wherein the one bit parallel inputs comprise retirement bits inside a hardware retirement logic structure.

12. The parallel adder circuit of claim 7 , wherein the first stage further comprises a mix of four to one and two to one adders, and wherein inputs that are not fed through the first stage are fed into subsequent stages to optimize the parallel adder circuit using the propagation delay differences of the subsequent stages.

13. A method for fast parallel adder processing, the method comprising:
receiving parallel inputs from a communications path, wherein each input comprises one bit;
adding the parallel inputs using a parallel structure, wherein the parallel structure is configured to accelerate the adding by utilizing a characteristic that the parallel inputs are one bit each, wherein the parallel structure comprises a first stage and a second stage, wherein the first stage comprises a four to one adder, wherein four one bit inputs are summed to produce one output comprising a three bit non-redundant result; and
transmitting resulting outputs from the adding to a subsequent stage.

14. The method of claim 13 , wherein the one bit parallel inputs comprise valid bits inside a hardware decoder.

15. The method of claim 13 , wherein the one bit parallel inputs comprise valid bits inside a hardware allocator.

16. The method of claim 13 , wherein the one bit parallel inputs comprise ready bits inside a hardware dispatch logic structure.

17. The method of claim 13 , wherein the one bit parallel inputs comprise retirement bits inside a hardware retirement logic structure.

18. The method of claim 13 , wherein the a first stage further comprises a mix of four to one and two to one adders, and wherein inputs that are not fed through the first stage are fed into subsequent stages to take advantage of propagation delay differences of the subsequent stages.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F7/5045 Primary

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