Source/drain contact depth control

Patent metadata

Field	Value
Publication number	US-10991796-B2
Application number	US-201816231671-A
Country	US
Kind code	B2
Filing date	Dec 24, 2018
Priority date	Dec 24, 2018
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

First claim

What is claimed is:

1. A method of fabricating a device, comprising:
providing a semiconductor structure disposed over a semiconductor substrate, the semiconductor structure comprising (i) a semiconductor fin comprising alternating channel and source/drain regions, (ii) a shallow trench isolation layer disposed over the semiconductor substrate laterally adjacent to a lower portion of the fin and within a fin cut opening between cut ends of the fin, (iii) an oxide layer disposed directly over and extending into the shallow trench isolation layer within the fin cut opening; and
forming a liner completely filling a space defined by the oxide layer within the fin cut opening, wherein the oxide layer extends above the shallow trench isolation layer and a side surface of the oxide layer above the shallow trench isolation layer abuts a side wall spacer, the space forming a hollow extending from above the shallow trench isolation layer and into the shallow trench isolation layer, the liner completely filling the hollow, the liner further defining sidewalls and a bottom of a first trench over the shallow trench isolation layer, the first trench having a bottom surface above a top surface of the shallow trench isolation layer and defined by a top surface of the oxide layer.

2. The method of claim 1 wherein the liner is conformal liner.

3. The method of claim 1 , further comprising source/drain junctions disposed over the source/drain regions of the semiconductor fin.

4. The method of claim 1 , wherein the top surface of the oxide layer is disposed above a bottom surface of the source/drain regions.

5. The method of claim 1 wherein the forming of the liner comprises atomic layer deposition.

6. The method of claim 1 wherein the liner comprises silicon nitride.

7. A semiconductor device, comprising:
a semiconductor fin comprising alternating channel and source/drain regions disposed over a semiconductor substrate;
a shallow trench isolation layer disposed over the semiconductor substrate laterally adjacent to a lower portion of the fin and within a fin cut opening between cut ends of the fin;
an oxide layer disposed directly over and extending into the shallow trench isolation layer within the fin cut opening; and
a conformal liner completely filling a space defined by the oxide layer within the fin cut opening, wherein the oxide layer extends above the shallow trench isolation layer and a side surface of the oxide layer above the shallow trench isolation layer abuts a side wall spacer, the space forming a hollow extending from above the shallow trench isolation layer and into the shallow trench isolation layer, the liner completely filling the hollow, the conformal liner further defining sidewalls and a bottom of a first trench over the shallow trench isolation layer, the first trench having a bottom surface above a top surface of the shallow trench isolation layer and defined by a top surface of the oxide layer.

8. The semiconductor device of claim 7 , further comprising source/drain junctions disposed over the source/drain regions of the semiconductor fin.

9. The semiconductor device of claim 8 , wherein a top surface of the oxide layer is disposed above a bottom surface of the source/drain junctions.

10. The semiconductor device of claim 7 , wherein the shallow trench isolation layer and the oxide layer each comprise silicon dioxide.

Assignees

• Globalfoundries Us Inc

Inventors

• Hu Lin
• Basker Veeraraghavan S
• Greene Brian J
• Zhao Kai
• Jaeger Daniel
• Tabakman Keith
• Nassar Christopher

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/0243

  using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability · CPC title