Vertical vacuum channel transistor

US10991537B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10991537-B2
Application numberUS-201916402302-A
CountryUS
Kind codeB2
Filing dateMay 3, 2019
Priority dateMay 3, 2019
Publication dateApr 27, 2021
Grant dateApr 27, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.

First claim

Opening claim text (preview).

What is claimed is: 1. A vertical vacuum channel transistor, comprising: a sharp tip structure comprising two tip portions, wherein one tip portion of the two tip portions is an emitter of the vertical vacuum channel transistor and another tip portion of the two tip portions is a collector of the vertical vacuum channel transistor; a vacuum channel between the two tip portions; and a gate of the vertical vacuum channel transistor, wherein a metal contact for each of the emitter, the collector and the gate of the vertical vacuum channel transistor is formed in a respective trench for each of the emitter, the collector and the gate of the vertical vacuum channel transistor that each extend downward in a vertical direction from a common top surface, wherein the two tip portions are formed from a silicon germanium (SiGe) material, wherein the silicon germanium (SiGe) material is a portion of an inverted T-shaped fin structure, and further comprising: a bottom spacer formed on a horizontal surface of the inverted T-shaped fin structure; a high-K dielectric layer formed on sidewalls of the inverted T-shaped fin structure; and a metal gate layer formed on the high-K dielectric layer, wherein the high-K dielectric layer is also formed on a top surface of the bottom spacer. 2. The vertical vacuum channel transistor of claim 1 , wherein the one tip portion and the another tip portion are separated by the vacuum channel that is less than 150 nm in length. 3. The vertical vacuum channel transistor of claim 1 , where the bottom spacer is formed from a silicon nitride (SiN) material. 4. The vertical vacuum channel transistor of claim 1 , wherein the bottom spacer is an isolation layer that separates the gate and the metal contact for the emitter. 5. A vertical vacuum channel transistor, comprising: a sharp tip structure comprising two tip portions, wherein one tip portion of the two tip portions is an emitter of the vertical vacuum channel transistor and another tip portion of the two tip portions is a collector of the vertical vacuum channel transistor; a vacuum channel between the two tip portions; and a gate of the vertical vacuum channel transistor, wherein the two tip portions are formed from a silicon germanium (SiGe) material, and wherein the one tip portion and the another tip portion are separated by the vacuum channel that is less than 150 nm in length, wherein the silicon germanium (SiGe) material is a portion of an inverted T-shaped fin structure, and further comprising: a bottom spacer formed on a horizontal surface of the inverted T-shaped fin structure; a high-K dielectric layer formed on sidewalls of the inverted T-shaped fin structure; and a metal gate layer formed on the high-K dielectric layer, wherein the high-K dielectric layer is also formed on a top surface of the bottom spacer. 6. The vertical vacuum transistor of claim 5 , where the bottom spacer is formed from a silicon nitride (SiN) material. 7. The vertical vacuum channel transistor of claim 5 , wherein the bottom spacer is an isolation layer that separates the gate and a metal contact for the emitter.

Assignees

Inventors

Classifications

  • being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

  • H01J21/105Primary

    with microengineered cathode and control electrodes, e.g. Spindt-type · CPC title

  • Cold cathodes, e.g. field-emissive cathode · CPC title

  • Manufacture of leading-in conductors · CPC title

  • H01J19/44Primary

    Insulation between electrodes or supports within the vacuum space · CPC title

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Frequently asked questions

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What does patent US10991537B2 cover?
A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the s…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01J21/105. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 27 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).