Multi-deck three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-10985142-B2
Application number	US-202016785571-A
Country	US
Kind code	B2
Filing date	Feb 8, 2020
Priority date	Dec 18, 2018
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck above the substrate, a first channel structure, a first inter-deck plug above and in contact with the first channel structure, a second memory deck above the first inter-deck plug, and a second channel structure above and in contact with the first inter-deck plug. The first memory deck includes a first plurality of interleaved conductor layers and dielectric layers. The first channel structure extends vertically through the first memory deck. The first inter-deck plug includes single-crystal silicon. The second memory deck includes a second plurality of interleaved conductor layers and dielectric layers. The second channel structure extends vertically through the second memory deck.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a substrate;
a first memory deck comprising a first plurality of interleaved conductor layers and dielectric layers above the substrate;
a first channel structure extending vertically through the first memory deck, the first channel structure comprising an upper plug comprising polysilicon at an upper end of the first channel structure and a first memory film and a first semiconductor channel along a sidewall of the first channel structure;
a first inter-deck plug comprising single-crystal silicon and that is (i) above and in contact with the first channel structure and (ii) above and in contact with the upper plug of the first channel structure;
a second memory deck comprising a second plurality of interleaved conductor layers and dielectric layers above the first inter-deck plug; and
a second channel structure extending vertically through the second memory deck and that is above and in contact with the first inter-deck plug.

2. The 3D memory device of claim 1 , wherein a thickness of the first inter-deck plug is between about 1 μm and about 100 μm.

3. The 3D memory device of claim 1 , wherein:
the first channel structure comprises a first memory film and a first semiconductor channel along a sidewall of the first channel structure; and
the first inter-deck plug is above and in contact with the first semiconductor channel of the first channel structure.

4. The 3D memory device of claim 1 , further comprising a dielectric vertically between the first and second memory decks and that surrounds the first inter-deck plug.

5. The 3D memory device of claim 1 , further comprising a bonding interface between the first memory deck and the first inter-deck plug.

6. The 3D memory device of claim 1 , further comprising a slit structure extending vertically through the first and second memory decks to the substrate.

7. The 3D memory device of claim 1 , further comprising:
an interconnect layer above the second memory deck; and
a through array contact (TAC) extending vertically through the first and second memory decks and electrically connected to the interconnect layer.

8. The 3D memory device of claim 7 , wherein the interconnect layer comprises a bit line.

9. The 3D memory device of claim 1 , further comprising:
a second inter-deck plug comprising single-crystal silicon and that is above and in contact with the second channel structure;
a third memory deck comprising a third plurality of interleaved conductor layers and dielectric layers above the second inter-deck plug; and
a third channel structure extending vertically through the third memory deck and that is above and in contact with the second inter-deck plug.

10. A three-dimensional (3D) memory device, comprising:
a substrate;
a first memory deck comprising a first plurality of interleaved conductor layers and dielectric layers above the substrate;
a first channel structure extending vertically through the first memory deck;
a first inter-deck plug above and in contact with the first channel structure;
a second memory deck comprising a second plurality of interleaved conductor layers and dielectric layers above the first inter-deck plug;
a second channel structure extending vertically through the second memory deck and that is above and in contact with the first inter-deck plug; and
a bonding interface between the first memory deck and the first inter-deck plug.

11. The 3D memory device of claim 10 , wherein the first inter-deck plug comprises single-crystal silicon.

12. The 3D memory device of claim 11 , wherein a thickness of the first inter-deck plug is between about 1 μm and about 100 μm.

13. The 3D memory device of claim 11 , wherein:
the first channel structure comprises an upper plug comprising polysilicon at an upper end of the first channel structure and a first memory film and a first semiconductor channel along a sidewall of the first channel structure; and
the first inter-deck plug is above and in contact with the upper plug of the first channel structure.

14. The 3D memory device of claim 10 , wherein:
the first channel structure comprises a first memory film and a first semiconductor channel along a sidewall of the first channel structure; and
the first inter-deck plug is above and in contact with the first semiconductor channel of the first channel structure.

15. The 3D memory device of claim 10 , further comprising a dielectric vertically between the first and second memory decks and that surrounds the first inter-deck plug.

16. The 3D memory device of claim 10 , further comprising a slit structure extending vertically through the first and second memory decks to the substrate.

17. The 3D memory device of claim 10 , further comprising:
an interconnect layer above the second memory deck; and
a through array contact (TAC) extending vertically through the first and second memory decks and electrically connected to the interconnect layer.

18. The 3D memory device of claim 17 , wherein the interconnect layer comprises a bit line.

19. The 3D memory device of claim 11 , further comprising:
a second inter-deck plug comprising single-crystal silicon and that is above and in contact with the second channel structure;
a third memory deck comprising a third plurality of interleaved conductor layers and dielectric layers above the second inter-deck plug; and
a third channel structure extending vertically through the third memory deck and that is above and in contact with the second inter-deck plug.

20. A three-dimensional (3D) memory device, comprising:
a substrate;
a first memory deck comprising a first plurality of interleaved conductor layers and dielectric layers above the substrate;
a first channel structure extending vertically through the first memory deck;
a first inter-deck plug comprising single-crystal silicon and that is above and in contact with an upper plug comprising polysilicon at an upper end of the first channel structure;
a second memory deck comprising a second plurality of interleaved conductor layers and dielectric layers above the first inter-deck plug; and
a second channel structure extending vertically through the second memory deck and that is above and in contact with the first inter-deck plug.

21. The 3D memory device of claim 20 , further comprising a bonding interface between the first inter-deck plug and the upper plug.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xiao li hong

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/301

  Bonding techniques, e.g. hybrid bonding · CPC title

• H10W80/033

  by chemical means, e.g. etching · CPC title