Hybrid logical to physical caching scheme

Patent metadata

Field	Value
Publication number	US-10983918-B2
Application number	US-201916294427-A
Country	US
Kind code	B2
Filing date	Mar 6, 2019
Priority date	Dec 31, 2018
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

First claim

What is claimed is:

1. A system comprising:
a non-transitory storage device including firmware having stored instructions, executable by a processing device, to perform operations to:
control access to a logical to physical (L2P) cache in a storage device and a L2P changelog in the storage device with the L2P cache being different from the L2P changelog, the L2P changelog containing pairs of a logical block address and a physical address, the logical block address mapped to the physical address in a memory system;
access a page pointer table in the L2P cache, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog; and
load the page pointer table into the L2P cache from the L2P changelog, based on the page pointer table being accessed in the L2P changelog a number of times in a specified timeframe equal to or greater than a threshold number of accesses in the specified timeframe.

2. The system of claim 1 , wherein the L2P changelog is arranged as a clustering of page pointer tables, with each page pointer table having one or more pairs of a logical block address and a physical address.

3. The system of claim 1 , wherein the storage device is a volatile memory storage device.

4. The system of claim 1 , wherein the operations include, for performance of another write operation in the memory system, an access of another page pointer table, with the other page pointer table disposed in the L2P changelog, to obtain another physical address mapped to a specified logical block address from a host for the other write operation.

5. The system of claim 1 , wherein the operations include:
association of a cold status or a hot status to each page pointer table in the L2P cache;
identification of a number, M, of page pointer tables in the L2P cache as having status of being M coldest of the page pointer tables in the L2P cache, M being a positive integer; and
a flush of the M page pointer tables in the L2P cache to the memory system, making M slots in the L2P cache available to load new page pointer tables from the L2P changelog, the new page pointer tables being new with respect to the L2P cache.

6. The system of claim 5 , wherein the operations include a selection of the number M to maximize memory system parallelism with respect to channels to access the memory system.

7. The system of claim 1 , wherein the operations include a loading of a selected page pointer table into the L2P cache from the L2P changelog based on the selected page pointer table being filled with a number, k, of elements, k being a positive integer.

8. The system of claim 7 , wherein the operations include initiation of the loading of the selected page pointer table into the L2P cache from the L2P changelog based on arrival of a k+1 element for the selected page pointer table.

9. A system comprising:
a memory device;
a storage device having a logical to physical (L2P) cache and a L2P changelog with the L2P cache being different from the L2P changelog, the L2P changelog containing pairs of a logical block address and a physical address, the logical block address mapped to the physical address in the memory device; and
firmware having stored instructions, executable by a processing device, to perform operations to:
control access to the L2P cache and the L2P changelog;
access a page pointer table in the L2P cache, for performance of a write operation in the memory device, to obtain a physical address mapped to a specified logical block address from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog; and
progressively configure the L2P cache with page pointer tables loaded into the L2P cache from the L2P changelog in which, prior to loading into the L2P cache, the page pointer tables have been accessed in the L2P changelog a number of times greater than a threshold number of accesses in a specified number of latest host accesses.

10. The system of claim 9 , wherein the storage device is a random access memory.

11. The system of claim 9 , wherein the L2P changelog is arranged as a clustering of page pointer tables, with each page pointer table having one or more pairs of a logical block address and a physical address.

12. The system of claim 9 , wherein the storage device is a volatile memory storage device.

13. The system of claim 9 , wherein the operations include, for performance of another write operation in the memory system, an access of another page pointer table, with the other page pointer table disposed in the L2P changelog, to obtain another physical address mapped to a specified logical block address from a host for the other write operation.

14. The system of claim 9 , wherein the operations include control of a loading of selected page pointer tables into the L2P cache from the L2P changelog by use of a coldness index of the page pointer tables in the L2P cache prior to initiating the loading of the selected page pointer tables from the L2P cache.

15. The system of claim 9 , wherein the operations include:
a loading of a selected page pointer table into the L2P cache from the L2P changelog based on the selected page pointer table being filled with a number, k, of elements, k being a positive integer;
an initiation of the loading of the selected page pointer table into the L2P cache from the L2P changelog based on arrival of a k+1 element for the selected page pointer table; and
a removal of the selected page pointer table from a pool of lists of the page pointer tables in the L2P changelog.

16. A method comprising:
controlling access to a logical to physical (L2P) cache in a storage device and a L2P changelog in the storage device with the L2P cache being different from the L2P changelog, the L2P changelog containing pairs of a logical block address and a physical address, the logical block address mapped to the physical address in a memory system;
accessing a page pointer table in the L2P cache, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog; and
progressively configuring the L2P cache with page pointer tables loaded into the L2P cache from the L2P changelog in which, prior to loading into the L2P cache, the page pointer tables have been accessed in the L2P changelog a number of times greater than a threshold number of accesses in a specified number of latest host accesses.

17. The method of claim 16 , wherein the method includes arranging the L2P changelog as a clustering of page pointer tables, with each page pointer table having one or rrore pairs of a logical block address and a physical address.

18. The method of claim 16 , wherein the storage device is a volatile memory storage device.

19. The method of claim 16 , wherein the method includes using a coldness index of the page pointer tables in the L2P cache to control loading selected page pointer tables into the L2P cache from the L2P changelog.

20. The method of claim 16 , wherein the method includes:
loading a specific page pointer table from a memory device of the memory system into the L2P cache, in response to an element received for inclusion in the specific page pointer table, the specific page pointer table filled with a maximum numbe

Assignees

• Micron Technology Inc

Inventors

• Manganelli Carminantonio
• Weinberg Yoav
• Sassara Alberto
• Papa Paolo
• Esposito Luigi
• D'Eliseo Giuseppe
• Della Monica Angelo
• Iaculo Massimo

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/0873 Primary

  Mapping of cache memory to specific storage devices or parts thereof · CPC title