Array broadcast and reduction systems and methods

Patent metadata

Field	Value
Publication number	US-10983793-B2
Application number	US-201916369846-A
Country	US
Kind code	B2
Filing date	Mar 29, 2019
Priority date	Mar 29, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

The present disclosure is directed to systems and methods of performing one or more broadcast or reduction operations using direct memory access (DMA) control circuitry. The DMA control circuitry executes a modified instruction set architecture (ISA) that facilitates the broadcast distribution of data to a plurality of destination addresses in system memory circuitry. The broadcast instruction may include broadcast of a single data value to each destination address. The broadcast instruction may include broadcast of a data array to each destination address. The DMA control circuitry may also execute a reduction instruction that facilitates the retrieval of data from a plurality of source addresses in system memory and performing one or more operations using the retrieved data. Since the DMA control circuitry, rather than the processor circuitry performs the broadcast and reduction operations, system speed and efficiency is beneficially enhanced.

First claim

What is claimed:

1. A direct memory access (DMA) system, comprising:
DMA control circuitry coupleable to memory circuitry, the DMA control circuitry including:
data broadcast logic to cause a performance of a data broadcast instruction to:
cause a read of a first data value from a memory location in the memory circuitry; and
cause a data broadcast operation of the first data value to each of a plurality of memory addresses, wherein a first one of the plurality of memory addresses is a base memory address location included in the data broadcast instruction and each successive one of the plurality of memory addresses is defined by an increment by a defined memory address offset also included in the data broadcast instruction with respect to a previous one of the plurality of memory addresses;

array broadcast logic to cause a performance of an array broadcast instruction to:
cause a read of an array that includes a defined number of elements from at least one memory location in the memory circuitry; and
cause an array broadcast operation of the array to each of a plurality of memory addresses, wherein a first one of the plurality of memory addresses is a base memory address location included in the array broadcast instruction and each successive one of the plurality of memory addresses is defined by an increment by a defined memory address offset also included in the array broadcast instruction with respect to a previous one of the plurality of memory addresses; and
array reduction logic to cause a performance of an array reduction instruction to:
perform one or more operations to generate an output value using respective values stored at each of a plurality of memory address locations, wherein a first one of the plurality of memory address locations is a base memory address location included in the array reduction instruction and each successive one of the plurality of memory address locations is defined by an increment by a defined memory address offset included in the array reduction instruction with respect to a previous one of the plurality of memory address locations.

2. The system of claim 1 , the data broadcast logic to further:
generate the data broadcast instruction, the data broadcast instruction having a format that includes:
a first data field that includes information representative of a pointer to a memory address location containing the defined memory address offset;
a second data field that includes information representative of a memory address location containing the first data value;
a third data field that includes information representative of a defined number of memory addresses included in the plurality of memory addresses; and
a fourth data field that includes information indicative of the base memory address location.

3. The system of claim 1 , the data broadcast logic to further:
generate the data broadcast instruction having a format that includes:
a data field that includes information representative of a memory address location containing a second data value; and
perform a first compare-overwrite operation, such that if existing data at respective ones of each of the plurality of memory addresses matches the second data value, the first data value is to replace the existing data at the respective memory address.

4. The system of claim 3 the data broadcast logic to further:
perform a second compare-overwrite operation, such that if the existing data at respective ones of each of the plurality of memory addresses differs from the second data value, the existing data is retained at the respective memory address.

5. The system of claim 1 , the array broadcast logic to further:
generate the array broadcast instruction, the array broadcast instruction having a format that includes:
a first data field that includes information representative of a pointer to a memory address location containing the defined memory address offset;
a second data field that includes information representative of the memory address location containing the elements included in the array broadcast to each of the plurality of memory addresses;
a third data field that includes information representative of a defined number of memory addresses included in the plurality of memory addresses;
a fourth data field that includes information representative of the defined number of elements included in the array broadcast to each of the plurality of memory addresses; and
a fifth data field that includes information representative of the base memory address location.

6. The system of claim 1 , the array reduction logic to further:
generate the array reduction instruction, the array reduction instruction having a format that includes:
a first data field that includes information representative of a pointer to a memory address location containing the defined memory address offset;
a second data field that includes information representative of a memory address location to receive the output value;
a third data field that includes information representative of a number of memory addresses included in the plurality of memory address locations that contain a value used in the one or more operations; and
a fourth data field that includes information representative of the base memory address location.

7. The system of claim 1 wherein, in each of the data broadcast instruction, the array broadcast instruction, and the array reduction instruction the DMA control circuitry further includes:
a 15-bit DMA type field that includes information indicative of a direct memory access type associated with the respective instruction.

8. The system of claim 7 wherein, in the 15-bit DMA type field, the DMA control circuitry further includes:
information indicative of an operation performed using data in a second instruction and the data stored at the respective memory address.

9. A non-transitory storage device that includes instructions that, when executed by direct memory access (DMA) control circuitry, cause the DMA control circuitry to:
cause data broadcast logic to execute a data broadcast instruction to:
read a first data value at a memory location in memory circuitry; and
broadcast the first data value to each of a plurality of memory addresses, wherein a first one of the plurality of memory addresses is at a base memory address location included in the data broadcast instruction and each successive one of the plurality of memory addresses is defined by an increment by a defined memory address offset also included in the data broadcast instruction with respect to a previous one of the plurality of memory addresses;

cause array broadcast logic to execute an array broadcast instruction to:
read an array that includes a defined number of elements at a memory location in memory circuitry; and
broadcast the array to each of a plurality of memory addresses, wherein a first one of the plurality of memory addresses is at a base memory address location included in the array broadcast instruction and each successive one of the plurality of memory addresses is defined by an increment by a defined memory address offset also included in the array broadcast instruction with respect to a previous one of the plurality of memory addresses; and

cause array reduction logic to execute an array reduction instruction to:
perform one or more operations to generate an output value using respective values stored at each of a plurality of memory address locations, wherein a first one of the plurality of memory address locations is a base memory address location included in the array reduction instruction and each successive one of the plurality of memory address locations is defined by an increment by a defined memory address offset i

Assignees

• Intel Corp

Inventors

• Fryman Joshua
• More Ankit
• Howard Jason
• Pawlowski Robert
• Demir Yigit
• Pepperling Nick
• Petrini Fabrizio
• Aananthakrishnan Sriram
• Smith Shaden

Classifications

• G06F9/30149

  of variable length instructions · CPC title

• G06F9/30105

  Register structure · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G11C8/04 Primary

  using a sequential addressing device, e.g. shift register, counter · CPC title