Large-scale matrix restructuring and matrix-scalar operations
US-12455738-B2 · Oct 28, 2025 · US
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More Ankit patents
More Ankit is listed as an inventor on 43 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | More Ankit |
| Total patents | 43 |
| First publication | Mar 15, 2016 |
| Latest publication | Oct 28, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
In-network multicast operations
US-12388712-B2 · Aug 12, 2025 · US
Determining shared exponent values for shared exponent floating point data types
US-2024402993-A1 · Dec 5, 2024 · US
Techniques for acceleration of a prefix-scan operation
US-12153932-B2 · Nov 26, 2024 · US
Assigning workloads to physical resources in spatial architectures
US-2024303117-A1 · Sep 12, 2024 · US
Method and apparatus for compressing and decompressing sparse data sets
US-11989414-B2 · May 21, 2024 · US
Compression circuits and methods using tree based encoding of bit masks
US-11942970-B2 · Mar 26, 2024 · US
Method and apparatus for compression multiplexing for sparse computations
US-11848689-B2 · Dec 19, 2023 · US
Sparsifying vectors for neural network models based on overlapping windows
US-2023334284-A1 · Oct 19, 2023 · US
Method and apparatus for compressing and decompressing sparse data sets
US-2023333739-A1 · Oct 19, 2023 · US
Recent patents
Latest publications not already listed above.
Method and apparatus for compression multiplexing for sparse computations
US-2023318620-A1 · Oct 5, 2023 · US
Compression circuits and methods using tree based encoding of bit masks
US-2023283296-A1 · Sep 7, 2023 · US
Method and apparatus for compressing and decompressing sparse data sets
US-11720252-B1 · Aug 8, 2023 · US
Memory system architecture for multi-threaded processors
US-11630691-B2 · Apr 18, 2023 · US
Sparsifying narrow data formats for neural networks
US-2022405571-A1 · Dec 22, 2022 · US
Multithreaded processor core with hardware-assisted task scheduling
US-11360809-B2 · Jun 14, 2022 · US
Large-scale matrix restructuring and matrix-scalar operations
US-2022100508-A1 · Mar 31, 2022 · US
In-network multicast operations
US-2021409265-A1 · Dec 30, 2021 · US
Memory system architecture for multi-threaded processors
US-2021389984-A1 · Dec 16, 2021 · US
Memory system architecture for multi-threaded processors
US-11106494-B2 · Aug 31, 2021 · US
System, apparatus and method for barrier synchronization in a multi-threaded processor
US-11061742-B2 · Jul 13, 2021 · US
Techniques for acceleration of a prefix-scan operation
US-2021149683-A1 · May 20, 2021 · US
Systolic array accelerator systems and methods
US-11003619-B2 · May 11, 2021 · US
Array broadcast and reduction systems and methods
US-10983793-B2 · Apr 20, 2021 · US
Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications
US-10929132-B1 · Feb 23, 2021 · US
Hardware support for dual-memory atomic operations
US-2020401412-A1 · Dec 24, 2020 · US
Multi-processor system with configurable cache sub-domains and cross-die memory coherency
US-10795819-B1 · Oct 6, 2020 · US
Array broadcast and reduction systems and methods
US-2020310795-A1 · Oct 1, 2020 · US
Systolic array accelerator systems and methods
US-2020272596-A1 · Aug 27, 2020 · US
Memory system architecture for multi-threaded processors
US-2020104164-A1 · Apr 2, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 32 |
| Microsoft Technology Licensing Llc | 11 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30043 | 10 |
| G06F9/4881 | 7 |
| G06F9/3851 | 7 |
| H03M7/3066 | 7 |
| G06N3/0495 | 7 |