Systems and methods for suppressing undesirable voltage supply artifacts

Patent metadata

Field	Value
Publication number	US-10978897-B2
Application number	US-201815942968-A
Country	US
Kind code	B2
Filing date	Apr 2, 2018
Priority date	Apr 2, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

Systems and methods described herein provide a sensor integrated circuit (IC) having a high voltage bi-directional current source and disconnect switch that are configured to suppress undesirable voltage artifacts. The sensor IC can include a power pin for coupling to an external power supply, a reference pin, and a functional circuit. The bi-directional current source can be disposed in a current path between the power pin and an energy storage device and be configured to control a current flow to the energy storage device and a current flow from the energy storage device.

First claim

What is claimed:

1. A sensor integrated circuit having a power pin for coupling to an external power supply, a reference pin, and a functional circuit, comprising:
an energy storage device;
a current mirror comprising at least one MOSFET device and having a current path in series between the power pin and the energy storage device and configured to control a current flow to the energy storage device and a current flow from the energy storage device, wherein the current mirror is further configured to decouple the energy storage device from the power pin; and
a gate drive circuit coupled to a gate terminal of the MOSFET device and comprising:
at least one switch configured to be in a first state to turn off the MOSFET device or in a second state to turn on the MOSFET device; and
a comparison device having a first input configured to receive a voltage associated with the power pin and a second input configured to receive a voltage associated with the energy storage device, wherein the at least one switch is controlled by an output of the comparison device.

2. The sensor integrated circuit of claim 1 , wherein the current mirror comprises a pair of PMOS devices having a common gate connection and a common source connection.

3. The sensor integrated circuit of claim 1 , wherein the current path comprises a first current path and wherein the current mirror further comprises a second current path configured to establish a current to be mirrored through the MOSFET device when the at least one switch is in the second state.

4. The sensor integrated circuit of claim 1 , wherein the output of the comparison device causes the at least one switch to turn off the MOSFET device when the voltage at the power pin is less than the voltage associated with the energy storage device.

5. The sensor integrated circuit of claim 1 , wherein the output of the comparison device causes the at least one switch to turn on the MOSFET device and to conduct a mirrored current associated with the second current path when the voltage at the power pin is greater than or equal to the voltage associated with the energy storage device.

6. A sensor integrated circuit having a power pin for coupling to an external power supply, a reference pin, and a functional circuit, comprising:
energy storing means;
means for controlling current having a current path in series between the power pin and the energy storage means, the means for controlling current configured to control a current flow to the energy storage means and a current flow from the energy storage means, wherein the means for controlling current is further configured to decouple the energy storage means from the power pin, wherein the means for controlling current comprises at least one MOSFET device; and
a current generating means coupled to a gate terminal of the MOSFET device and comprising:
at least one switching means configured to be in a first state to turn off the MOSFET device or in a second state to turn on the MOSFET device; and
means for comparing having a first input configured to receive a voltage associated with the power pin and a second input configured to receive a voltage associated with the energy storage device, wherein the at least one switching means is controlled by an output of the means for comparing.

7. The sensor integrated circuit of claim 6 , wherein the means for controlling current comprises a pair of PMOS devices having a common gate connection and a common source connection.

8. The sensor integrated circuit of claim 6 , wherein the current path comprises a first current path and wherein the current generating means further comprises a second current path configured to establish a current to be mirrored through the MOSFET device when the at least one switching means is in the second state.

9. The sensor integrated circuit of claim 6 , wherein the output of the means for comparing causes the at least one switching means to turn off the MOSFET device when the voltage at the power pin is less than the voltage associated with the energy storage device.

10. The sensor integrated circuit of claim 6 , wherein the output of the means for comparing causes the at least one switching means to turn on the MOSFET device and to conduct a mirrored current associated with the second current path when the voltage at the power pin is greater than or equal to the voltage associated with the energy storing means.

Assignees

• Allegro Microsystems Llc

Inventors

• Tran Sam

Classifications

• H02J7/933

  the cycle being controlled or terminated in response to electric parameters · CPC title

• H02H3/18 Primary

  responsive to reversal of direct current · CPC title

• H02H3/202

  for DC systems · CPC title

• G01R19/16552

  in I.C. power supplies · CPC title

• G01R33/0023

  Electronic aspects, e.g. circuits for stimulation, evaluation, control; Treating the measured signals; calibration (G01R33/0017 takes precedence) · CPC title