Fabrication of a device

Patent metadata

Field	Value
Publication number	US-10978632-B2
Application number	US-201916252237-A
Country	US
Kind code	B2
Filing date	Jan 18, 2019
Priority date	Jan 18, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction.

First claim

The invention claimed is:

1. A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material, and wherein the method comprises:
in a masking phase, forming a mask on an underlying layer of the device, wherein the mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of said lengths of material, and wherein a respective section of each of at least two of said trenches either (a) narrows down, or (b) is separated by a discontinuity, at a position corresponding to the at least one junction;
in a selective area growth phase, growing, by selective-area-growth, material in the set of trenches to form the lengths of material on the underlying layer; and
joining the two or more lengths of material at the at least one junction.

2. The method of claim 1 , wherein said joining comprises merging by lateral growth of the material during the selective area growth phase.

3. The method of claim 1 , wherein said joining comprises, in a subsequent phase to the selective area growth phase, connecting the two or more lengths of material via an electrical conductor.

4. The method of claim 1 , wherein the at least one junction joins only two or three of the lengths of material; thus forming a T-junction.

5. The method of claim 1 , wherein at least four of said lengths of material are joined at the at least one junction, wherein a respective section of each of least four trenches either (a) narrows down, or (b) is separated by a discontinuity, at a position corresponding to the at least one junction, and wherein said joining comprises joining the at least four lengths of material at the at least one junction; thus forming a cross junction.

6. The method of claim 1 , wherein the device comprises a plurality of junctions each joining at least some of the lengths of material, wherein two or more respective lengths of material are joined at each respective junction, wherein the mask comprises, for each respective junction, a respective set of two or more trenches corresponding to the two or more respective lengths of material, wherein a respective section of each of the two or more respective trenches either (a) narrows down, or (b) is separated by a discontinuity, at a position corresponding to each respective junction, wherein said growing comprises, growing, by selective-area-growth, material in the respective sets of trenches to form the two or more respective lengths of material on the underlying layer, and wherein said joining comprises joining the two or more respective lengths of material at each respective junction.

7. The method of claim 1 , wherein the underlying layer is an underlying layer of a wafer.

8. The method of claim 1 , wherein the underlying layer is a substrate of the wafer.

9. The method of claim 1 , wherein the plurality of trenches are formed by etching the mask from the underlying layer.

10. The method of claim 1 , wherein a pattern of the plurality of trenches is defined by lithography.

11. The method of claim 1 , wherein the mask is an insulating mask.

12. The method of claim 1 , wherein the mask is a dielectric.

13. The method of claim 1 , wherein the underlying layer is an insulating material.

14. The method of claim 1 , wherein the material is a semiconductor.

15. The method of claim 1 , wherein the material is grown by epitaxy.

16. The method of claim 1 , comprising:
in a superconductor growth phase, growing a layer of superconductor material over at least some of the lengths of material.

17. The method of claim 16 , wherein the layer of superconductor material is applied using a particle beam.

18. The method of claim 16 , wherein the superconductor material is grown by epitaxy.

19. The method of claim 1 , wherein the device is a quantum device and wherein the lengths of material are nanowires.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Kallaher Raymond Leonard
• Gronin Sergei Vyatcheslavovich
• Gardner Geoffrey Charles

Classifications

• H10N69/00 Primary

  Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 · CPC title

• H10N60/128

  having three or more electrodes, e.g. transistor-like structures · CPC title

• H10N60/01 Primary

  Manufacture or treatment · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title