Formation of devices by epitaxial layer overgrowth

Patent metadata

Field	Value
Publication number	US-9934967-B2
Application number	US-201313737731-A
Country	US
Kind code	B2
Filing date	Jan 9, 2013
Priority date	Sep 19, 2008
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a conductive handle wafer, no junction of a photovoltaic cell being within the conductive handle wafer;
a first semiconductor layer comprising InGaAs over and directly bonded to the conductive handle wafer, the first semiconductor layer comprising a first p-n junction and having a first band gap;
a buffer layer comprising GaInP over and physically contacting the first semiconductor layer;
a second semiconductor layer comprising GaAs over and physically contacting the buffer layer, the second semiconductor layer comprising a second p-n junction and having a second band gap, the second band gap being greater than the first band gap;
a third semiconductor layer comprising InGaP over and physically contacting the second semiconductor layer, the third semiconductor layer comprising a third p-n junction and having a third band gap, the third band gap being greater than the second band gap; and
a carrier substrate connected to the third semiconductor layer, the carrier substrate operable to be removed from the third semiconductor layer, the carrier substrate comprising:
a first crystalline material comprising silicon;
an insulating layer having a thickness over and physically contacting the first crystalline material, the insulating layer having a trench extending to the first crystalline material, the trench having a height and a width, wherein the height exceeds the width; and
a second crystalline material comprising germanium disposed in the trench and physically contacting a top surface of the insulating layer, the second crystalline material being lattice mismatched to the first crystalline material, wherein substantially all defects arising from the lattice mismatch terminate in the trench, wherein the third semiconductor layer is in physical contact with the second crystalline material and is located over the defects located in the trench.

2. The semiconductor structure of claim 1 , wherein the first semiconductor layer is approximately 2 micrometers.

3. The semiconductor structure of claim 1 , wherein the conductive handle wafer comprises a metal.

4. The semiconductor structure of claim 1 , wherein the buffer layer has a graded composition.

5. The semiconductor structure of claim 1 , wherein wherein the second crystalline material adjoins a (110)-surface of the first crystalline material.

6. The semiconductor structure of claim 1 , wherein the second crystalline material includes p-type dopants.

7. The semiconductor structure of claim 1 , wherein a bandgap energy of the first semiconductor layer is about to eV, a bandgap energy of the second semiconductor layer is about 1.4 eV, and a bandgap energy of the third semiconductor layer is about 1.8 eV.

8. A semiconductor structure comprising:
a conductive handle wafer, no junction of a photovoltaic cell being within the conductive handle wafer;
a multi-junction photovoltaic cell on a first side of the conductive handle wafer, the multi junction photovoltaic cell comprising:
a first semiconductor material over and directly bonded to the conductive handle wafer, the first semiconductor material comprising InGaAs;
a graded buffer material over and physically contacting the first semiconductor material, the graded buffer material comprising GaInP;
a second semiconductor material over and physically contacting the graded buffer material, a bandgap energy of the second semiconductor material being greater than a bandgap energy of the first semiconductor material, the second semiconductor material comprising GaAs; and
a third semiconductor material over and physically contacting the second semiconductor material, a bandgap energy of the third semiconductor material being greater than the bandgap energy of the second semiconductor material, the third semiconductor material comprising InGaP; and

a carrier substrate connected to the third semiconductor layer, the carrier substrate operable to be removed from the third semiconductor layer, the carrier substrate comprising:
a first crystalline material comprising silicon;
an insulating layer having a thickness over the first crystalline material, the insulating layer having a trench extending to the first crystalline material, the trench having a height and a width, wherein the height exceeds the width; and
a second crystalline material comprising germanium disposed in the trench and on a top surface of the insulating layer, the second crystalline material being lattice mismatched to the first crystalline material, substantially all defects arising from the lattice mismatch terminating in the trench, wherein the third semiconductor layer is in physical contact with the second crystalline material and is located over the defects located in the trench.

9. The semiconductor structure of claim 8 , wherein no material comprising germanium is disposed between the conductive handle wafer and the first semiconductor material.

10. The semiconductor structure of claim 8 , wherein each of the first semiconductor material, the second semiconductor material, and the third semiconductor material comprises a III-V semiconductor compound.

11. The semiconductor structure of claim 8 , wherein the bandgap energy of the first semiconductor material is to eV, the bandgap energy of the second semiconductor material is 1.4 eV, and the bandgap energy of the third semiconductor material is 1.8 eV.

12. The semiconductor structure of claim 8 , wherein the second crystalline material is doped with p-type dopants.

13. The semiconductor structure of claim 8 , wherein the first semiconductor material is approximately 2 micrometers.

14. A semiconductor structure comprising:
a removable structure comprising:
a first substrate comprising a first crystalline material, the first crystalline material comprising silicon;
an insulating layer over and physically contacting the first substrate, the insulating layer having a trench formed therein, the trench extending to the first substrate, the trench having a height and a width, wherein the height exceeds the width; and
a second crystalline material comprising a first portion disposed in the trench and physically contacting the first substrate and further comprising a second portion over and physically contacting a top surface of the insulating layer, the second portion of the second crystalline material forming a layer having a thickness from the top surface of the insulating layer and in a direction perpendicular to the top surface of the insulating layer, the second crystalline material being lattice mismatched to the first crystalline material, the second crystalline material comprising germanium, wherein substantially all defects in the second crystalline material arising from the lattice mismatch are limited to being in the first portion of the second crystalline material, wherein the first substrate, the insulating layer, and the second crystalline material are operable to be removed;

a first semiconductor material disposed over the defects in the first portion of the second crystalline material and physically contacting the second portion of the second crystalline material, the first semiconductor material comprising InGaP;
a second semiconductor material disposed over and physically contacting the first semiconductor material, a bandgap energy of the first semiconductor material being greater than a bandgap energy of the second semiconductor material, the second semiconductor material comprising GaAs;
a buffer layer disposed over and physically contacting the second semiconductor material, the buffer layer comprising GaInP;
a third semiconductor m

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hydrick Jennifer M
• Li Jizhong
• Cheng Zhinyuan
• Fiorenza James
• Bai Jie
• Park Ji-Soo
• Lochtefeld Anthony J

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/3418

  Phosphides · CPC title

• H10P14/3221

  Arsenides · CPC title

• H10P14/3218

  Phosphides · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title