Fabrication of a quantum device

Patent metadata

Field	Value
Publication number	US-10777728-B2
Application number	US-201916252230-A
Country	US
Kind code	B2
Filing date	Jan 18, 2019
Priority date	Jan 18, 2019
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

In a masking phase, a first segment of an amorphous mask is formed on an underlying layer of a substrate. The first segment comprises a first set of trenches exposing the underlying layer. In the masking phase, a second segment of the amorphous mask is formed on the underlying layer. The second segment comprises a second set of trenches exposing the underlying layer. The segments are non-overlapping. An open end of one of the first set of trenches faces an open end of one of the second set of trenches, but the ends are separated by a portion of the amorphous mask. In a semiconductor growth phase, semiconductor material is grown, by selective area growth, in the first and second sets of trenches to form first and second sub-networks of nanowires on the underlying layer. The first and second sub-networks of nanowires are joined to form a single nanowire network.

First claim

The invention claimed is:

1. A method of fabricating a quantum device, the method comprising:
in a masking phase, forming a first segment of an amorphous mask on an underlying layer of a substrate, wherein the first segment comprises a first set of trenches exposing the underlying layer;
in the masking phase, forming a second segment of the amorphous mask on the underlying layer, wherein the second segment comprises a second set of trenches exposing the underlying layer, wherein the first and second segments are non-overlapping, and wherein an open end of one of the first set of trenches faces an open end of one of the second set of trenches, but the ends being separated by a portion of the amorphous mask;
in a semiconductor growth phase, growing, by selective-area-growth, semiconductor material in the first and second sets of trenches to form first and second sub-networks of nanowires on the underlying layer; and
joining the first and second sub-networks of nanowires to form a single nanowire network on the underlying layer.

2. The method of claim 1 , wherein said joining comprises merging by lateral growth of the semiconductor material during the semiconductor growth phase.

3. The method of claim 1 , wherein said joining comprises, in a subsequent phase to the semiconductor growth phase, connecting the open end of the one of the first set of trenches with the open end of the one of the second set of trenches via an electrical conductor or superconductor.

4. The method of claim 1 , wherein the underlying layer is a wafer of the substrate.

5. The method of claim 1 , wherein the open end of first trench of the first set is separated from the open end of the first trench of the second set at a non-active region of the nanowire network.

6. The method of claim 1 , wherein the first and second network of trenches are formed by etching the amorphous mask from the underlying layer.

7. The method of claim 1 , wherein a respective pattern of the first and second trenches is defined by lithography.

8. The method of claim 1 , where said growing of the semiconductor material comprises:
depositing a respective droplet of a first material in the first and second sets of trenches;
then, depositing a second material to convert the first material into the semiconductor material.

9. The method of claim 8 , wherein the first material is Indium, wherein the second material is Antimony, and wherein the semiconductor material is Indium antimonide.

10. The method of claim 1 , wherein the semiconductor material is grown by epitaxy or evaporation.

11. The method of claim 1 , comprising:
in a superconductor growth phase, growing a layer of superconductor material over at least part of the nanowire network.

12. The method of claim 1 , wherein a layer of superconductor material is applied using a particle beam.

13. The method of claim 12 , wherein the superconductor material is grown by epitaxy.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Aseev Pavel
• Caroff-Gaonac'H Philippe

Classifications

• H10N60/85

  Superconducting active materials · CPC title

• H10N60/01

  Manufacture or treatment · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10N60/10 Primary

  Junction-based devices · CPC title