Manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-10978428-B2
Application number	US-201916678288-A
Country	US
Kind code	B2
Filing date	Nov 8, 2019
Priority date	May 7, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer;
flipping the cell chip;
exposing a rear surface of the source layer by removing the first substrate from the cell chip;
performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer;
forming a peripheral circuit chip including a second substrate and a circuit on the second substrate; and
bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

2. The method of claim 1 , wherein the performing of the surface treatment on the source layer comprises:
implanting a dopant into the source layer; and
performing heat treatment on the source layer into which the dopant is implanted.

3. The method of claim 1 , wherein the forming of the cell chip comprises:
forming the source layer on the first substrate;
patterning the source layer; and
forming the stacked structure on a patterned source layer.

4. The method of claim 1 , wherein the cell chip and the peripheral circuit chip are bonded so that the stacked structure is located between the source layer and the second substrate.

5. The method of claim 1 , wherein the surface treatment is performed on the source layer by irradiating the source layer with a laser beam incident on the source layer.

6. The method of claim 1 , wherein the source layer includes a polysilicon layer and a grain size of the polysilicon layer is increased by the surface treatment.

7. The method of claim 1 , further comprising patterning the source layer after performing the surface treatment on the rear surface of the source layer.

8. The method of claim 2 , wherein the dopant contains an N type impurity or a P type impurity.

9. The method of claim 1 , wherein the cell chip is formed so that the stacked structure is located on the patterned source layer.

10. The method of claim 9 , wherein the surface treatment is performed on a rear surface of the patterned source layer.

11. The method of claim 1 , wherein the cell chip further includes an insulating layer interposed between the first substrate and the source layer.

12. The method of claim 11 , wherein the exposing of the rear surface of the source layer comprises:
exposing the insulating layer by removing the first substrate; and
exposing the source layer by removing the insulating layer.

13. The method of claim 12 , wherein the insulating layer is removed by a wet etch process.

14. A method of manufacturing a semiconductor device, the method comprising:
forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer;
flipping the cell chip;
exposing a rear surface of the source layer by removing the first substrate from the cell chip;
irradiating the source layer with a laser beam incident on the rear surface of the source layer;
patterning the source layer onto which the laser beam is irradiated;
forming a peripheral circuit chip including a second substrate and a circuit on the second substrate; and
bonding the cell chip including a patterned source layer to the peripheral circuit chip.

15. The method of claim 14 , wherein the source layer includes a polysilicon layer and a grain size of the polysilicon layer is increased by laser irradiation.

16. A method of manufacturing a semiconductor device, the method comprising:
forming a cell chip including a first substrate, a patterned source layer on the first substrate, a stacked structure on the patterned source layer, and a channel layer passing through the stacked structure and coupled to the patterned source layer;
flipping the cell chip;
exposing the patterned source layer by removing the first substrate from the cell chip;
irradiating the patterned source layer with a laser beam incident on rear surfaces of the patterned source layer;
forming a peripheral circuit chip including a second substrate and a circuit on the second substrate; and
bonding the cell chip including the patterned source layer of which the laser beam is irradiated to the peripheral circuit chip.

17. The method of claim 16 , wherein the source layer includes a polysilicon layer and a grain size of the polysilicon layer is increased by laser irradiation.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jin Ha

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/041

  Thermally treating · CPC title