Radio-frequency loss reduction in photonic circuits

Patent metadata

Field	Value
Publication number	US-10976637-B2
Application number	US-201916269293-A
Country	US
Kind code	B2
Filing date	Feb 6, 2019
Priority date	Apr 16, 2015
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

In photonic integrated circuits implemented in silicon-on-insulator substrates, non-conductive channels formed, in accordance with various embodiments, in the silicon device layer and/or the silicon handle of the substrate in regions underneath radio-frequency transmission lines of photonic devices can provide breaks in parasitic conductive layers of the substrate, thereby reducing radio-frequency substrate losses.

First claim

The invention claimed is:

1. A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
depositing a dielectric material on top of the silicon device layer to form a cladding layer;
forming a waveguide within at least one of the silicon device layer or the cladding layer;
forming, within at least one of the silicon device layer or the silicon handle, one or more nonconductive channels extending to the buried oxide layer and running parallel to the waveguide; and
depositing, patterning, and etching electrode metals on top of the cladding layer to create a pair of electrodes of a transmission line running parallel to the waveguide, wherein the created electrodes are placed such that the one or more nonconductive channels are located in a region underneath the transmission line, overlapping with a gap defined between the electrodes but not extending beyond outer edges of the electrodes.

2. The method of claim 1 , wherein forming the waveguide comprises patterning and partially etching the silicon device layer to form a silicon rib waveguide therein prior to depositing the dielectric material.

3. The method of claim 1 , wherein forming the waveguide comprises bonding III-V material to the substrate and patterning and etching the deposited III-V material to form a III-V waveguide.

4. The method of claim 3 , wherein the III-V material is bonded to a planarized layer of dielectric material deposited on the silicon device layer and forming part of the cladding layer.

5. The method of claim 1 , wherein forming the one or more nonconductive channels comprises patterning and etching the silicon device layer down to the buried oxide layer to form one or more nonconductive channels in the silicon device layer prior to depositing the dielectric material.

6. The method of claim 1 , wherein forming the one or more nonconductive channels comprises flipping and aligning the substrate following the formation of the waveguide and the creation of the electrodes, and patterning and etching one or more back-side trenches into the silicon handle to form one or more nonconductive channels in the silicon handle.

7. A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
depositing a dielectric material on top of the silicon device layer to form a cladding layer;
forming a waveguide of a first photonic device and a waveguide of a second photonic device within at least one of the silicon device layer or the cladding layer;
forming, within at least one of the silicon device layer or the silicon handle, confined to a region encompassing only the first photonic device, one or more nonconductive channels extending to the buried oxide layer and running parallel to the waveguide of the first photonic device; and
depositing, patterning, and etching electrode metals on top of the cladding layer to create electrodes of a transmission line of the first photonic device on both sides of the waveguide of the first photonic device, wherein the created electrodes are placed such that the one or more nonconductive channels are located in a region underneath the transmission line, overlapping with a gap defined between the electrodes.

8. The method of claim 7 , wherein the one or more nonconductive channels comprise one or more channels formed in the silicon device layer and filled with the deposited dielectric material forming the cladding layer.

9. The method of claim 8 , wherein the electrodes comprise at least three electrodes defining at least two gaps between adjacent ones of the electrodes, and wherein the channels in the silicon device layer comprise at least two channels each laterally overlapping with one of the at least two gaps and not extending beyond outer edges of the pair of adjacent electrodes defining the respective gap.

10. The method of claim 8 , wherein forming the one or more channels in the silicon device layer comprises periodically removing material from the silicon device layer to form multiple channels.

11. The method of claim 7 , wherein the one or more nonconductive channels comprise one or more channels in the silicon handle.

12. The method of claim 7 , wherein forming the waveguide of the first photonic device comprises embedding a III-V waveguide in the cladding layer.

13. The method of claim 7 , wherein forming the waveguide of the first photonic device comprises patterning and partially etching the silicon device layer to form a silicon rib waveguide therein prior to depositing the dielectric material.

Assignees

• Aurrion Inc

Inventors

• Parker John
• Fish Gregory Alan
• Koch Brian R

Classifications

• H10F71/127

  The active layers comprising only Group III-V materials, e.g. GaAs or InP · CPC title

• H10F39/806

  Optical elements or arrangements associated with the image sensors · CPC title

• H01P3/026

  Coplanar striplines [CPS] · CPC title

• G02F1/2257

  the optical waveguides being made of semiconducting material · CPC title

• G02F1/2255 Primary

  controlled by a high-frequency electromagnetic component in an electric waveguide structure · CPC title