Radio-frequency loss reduction in photonic circuits

Patent metadata

Field	Value
Publication number	US-10241379-B1
Application number	US-201815987345-A
Country	US
Kind code	B1
Filing date	May 23, 2018
Priority date	Apr 16, 2015
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

In photonic integrated circuits implemented in silicon-on-insulator substrates, non-conductive channels formed, in accordance with various embodiments, in the silicon device layer and/or the silicon handle of the substrate in regions underneath radio-frequency transmission lines of photonic devices can provide breaks in parasitic conductive layers of the substrate, thereby reducing radio-frequency substrate losses.

First claim

The invention claimed is:

1. A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
patterning and partially etching the silicon device layer to form at least portions of waveguides in the silicon device layer;
following the partial etching, patterning and etching the silicon device layer down to the buried oxide layer to form one or more conductivity-breaking channels in the silicon device layer between the waveguides;
depositing a dielectric material on top of the etched silicon device layer to form a cladding layer;
embedding, in the cladding layer, III-V waveguides above the waveguides in the silicon device layer; and
depositing, patterning, and etching electrode metals on top of the cladding layer to create electrodes of a transmission line, wherein the created electrodes are placed such that the conductivity-breaking channels are located in a region underneath the transmission line, overlapping with a gap defined between the electrodes and not extending beyond outer edges of the electrodes.

2. The method of claim 1 , further comprising:
flipping the patterned substrate and patterning and etching the silicon handle to form back-side trenches therein in the region underneath the transmission line.

3. The method of claim 2 , further comprising:
filling the back-side trenches with a non-conductive polymer or dielectric.

4. The method of claim 2 , wherein the back-side trenches do not extend beyond the outer edges of the electrodes.

5. The method of claim 1 , wherein embedding III-V waveguides in the cladding layer comprises bonding III-V material to a planarized surface of dielectric material deposited on the silicon device layer, and patterning and etching the bonded III-V material to create the III-V waveguides.

6. The method of claim 1 , wherein the created transmission line comprises three or more electrodes defining two or more gaps between the electrodes, and wherein the conductivity-breaking channels in the silicon device layer are placed to each overlap with one of the two or more gaps without extending beyond outer edges of the electrodes defining the respective gap.

7. The method of claim 1 , wherein the waveguides in the silicon device layer together with the III-V waveguides thereabove form interferometric waveguide arms.

8. The method of claim 7 , wherein the interferometric waveguide arms are part of a Mach-Zehnder modulator.

9. The method of claim 1 , wherein the waveguides formed in the silicon device layer are rib waveguides, wherein partially etching the silicon device layer forms upper portions of the rib waveguides and wherein etching the silicon device layer down to the buried oxide layer forms lower portions of the rib waveguides.

10. A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
depositing, patterning, and etching dielectric and III-V layers to create a dielectric cladding on top of the silicon device layer and, embedded within the dielectric layer, one or more III-V optical waveguides;
creating, on top of the cladding, a transmission line comprising two electrodes defining a gap therebetween, the gap laterally overlapping with at least one of the one or more III-V optical waveguides; and
patterning and etching the silicon handle to form therein a nonconductive channel overlapping with the gap defined between the two electrodes and not extending beyond outer edges of the electrodes.

11. The method of claim 10 , further comprising:
prior to depositing, patterning, and etching the dielectric and III-V layers, patterning and etching the silicon device layer to form therein a nonconductive channel laterally overlapping with the gap defined between the two electrodes and not extending beyond outer edges of the electrodes.

12. The method of claim 10 , further comprising:
flipping and aligning the SOI substrate after creating the dielectric cladding, the one or more III-V optical waveguides, and the transmission line, but prior to patterning and etching the silicon handle.

13. The method of claim 10 , further comprising filling the nonconductive channel formed in the silicon handle with at least one of a dielectric material or a nonconductive polymer.

14. The method of claim 10 , wherein the created transmission line comprises three or more electrodes defining two or more gaps between the electrodes, and wherein the silicon handle is patterned and etched to form therein two or more nonconductive channels each overlapping with one of the two or more gaps and not extending beyond outer edges of the electrodes defining the respective gap.

15. A method of fabricating an integrated photonic circuit (PIC) from a silicon-on-insulator substrate comprising a silicon handle, a buried oxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried oxide layer, the method comprising:
patterning and etching at least one of the silicon device layer or one or more dielectric or III-V layers deposited above the silicon device layer to create optical components of a first photonic device and of one or more second photonic devices in at least one of the silicon device layer or the one or more dielectric or III-V layers;
creating a transmission line above an optical component of the first photonic device, the transmission line comprising two or more electrodes defining one or more gaps therebetween; and
patterning and etching at least one of the silicon device layer or the silicon handle to form therein one or more nonconductive channels each extending throughout the silicon device layer or silicon handle and overlapping with one of the one or more gaps, the one or more nonconductive channels being confined to a region encompassing only the first photonic device.

16. The method of claim 15 , wherein the one or more nonconductive channels comprise one or more channels formed in the silicon device layer, each of the one or more channels in the silicon device layer laterally overlapping with one of the one or more gaps and not extending beyond outer edges of a pair of adjacent electrodes defining the respective gap.

17. The method of claim 16 , wherein the one or more channels in the silicon device layer do not laterally overlap with the electrodes defining the respective gaps.

18. The method of claim 17 , wherein the one or more channels in the silicon device layer are narrower than the respective gaps.

19. The method of claim 18 , wherein the one or more channels in the silicon device layer comprise multiple channels formed underneath one of the one or more gaps, and wherein forming the multiple channels comprises periodic removal of material from the silicon device layer.

Assignees

• Aurrion Inc

Inventors

• Parker John
• Fish Gregory Alan
• Koch Brian R

Classifications

• G02F1/2255 Primary

  controlled by a high-frequency electromagnetic component in an electric waveguide structure · CPC title

• H01L27/14625

  Electricity · mapped topic

• H01L31/184

  Electricity · mapped topic

• G02F1/2257

  the optical waveguides being made of semiconducting material · CPC title

• H10F71/127

  The active layers comprising only Group III-V materials, e.g. GaAs or InP · CPC title