Automated test equipment (ATE) support framework for solid state device (SSD) odd sector sizes and protection modes

Patent metadata

Field	Value
Publication number	US-10976361-B2
Application number	US-201816227389-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Dec 20, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.

First claim

What is claimed is:

1. An automated test equipment (ATE) apparatus comprising:
a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes;
the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes; and
wherein the tester processor is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between the tester processor and the FPGA in a different manner.

2. The apparatus of claim 1 , wherein the system controller is operable to provide a graphical user interface (GUI) operable to allow a user to select one of the plurality of functional modes.

3. The apparatus of claim 1 , wherein the system controller is operable to configure the tester processor and the FPGA to test the DUT for each of the plurality of protection modes and each of the plurality of non-standard sector sizes.

4. The apparatus of claim 1 wherein the functional modes comprise four functional modes comprising a bypass mode, the hardware accelerator pattern generator mode, a hardware accelerator memory mode and a hardware accelerator packet builder mode.

5. The apparatus of claim 4 wherein, in the bypass mode, the tester processor is configured to generate all commands and data for coordinating testing of the DUT, and wherein the data comprises the protection information associated with the plurality of protection modes and sector data to fit each of the plurality of non-standard sector sizes.

6. The apparatus of claim 5 wherein, in the hardware accelerator pattern generator mode: the tester processor is configured to generate all commands for coordinating testing of the DUT; and the at least one hardware accelerator circuit of the FPGA generates test pattern data, wherein the test pattern data comprises the protection information associated with the plurality of protection modes and sector data to fit each of the plurality of non-standard sector sizes.

7. The apparatus of claim 5 wherein, in the hardware accelerator memory mode: the tester processor is configured to generate all commands for coordinating testing of the DUT; and the at least one hardware accelerator circuit of the FPGA performs a step selected from the group comprising: read the test pattern data from the memory device, write the test pattern data to the DUT and compare the data read from the DUT, wherein the test pattern data stored in the memory device comprises the protection information associated with the plurality of protection modes and sector data to fit each of the plurality of non-standard sector sizes.

8. The apparatus of claim 5 wherein, in the hardware accelerator packet builder mode, the at least one hardware accelerator circuit of the FPGA is configured to generate both test data and command data for coordinating testing of the DUT wherein the test pattern data comprises the protection information associated with the plurality of protection modes and sector data to fit each of the plurality of non-standard sector sizes.

9. The apparatus of claim 1 , wherein the system controller is operable to execute a Windows operating system.

10. The apparatus of claim 1 , wherein the tester processor is configured to execute a Linux operating system.

11. The apparatus of claim 1 , wherein the FPGA comprises an IP core, wherein the IP core is operable to be programmed to emulate a protocol, wherein the protocol is selected from a group consisting of: SATA or SAS.

12. The apparatus of claim 11 , wherein the IP core is operable to be re-programmed to emulate a different protocol.

13. The apparatus of claim 1 , wherein the DUT is a solid state device (SSD).

14. The apparatus of claim 13 , wherein the plurality of non-standard sector sizes can be selected from a group consisting of: 520+0, 4104+0, 528+0, and 4224+0.

15. The apparatus of claim 13 , wherein the plurality of protection modes can be selected from a group consisting of: 512+8 and 4096+8.

16. A method for testing using an automated test equipment (ATE) comprising:
transmitting instructions from a system controller of a computer system to a tester processor, wherein the system controller is communicatively coupled to a the tester processor and an FPGA, wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of DUTs, wherein each of the plurality of DUTs supports a plurality of non-standard sector sizes and a plurality of protection modes;
generating commands and data transparently from the tester processor for testing of a plurality of DUTs using a hardware accelerator circuit programmed within an FPGA, wherein the FPGA is communicatively coupled to the tester processor and wherein the hardware accelerator circuit is operable to test the plurality of DUTs, and wherein the hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes; and
operating the tester processor in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between the tester processor and the FPGA in a different manner.

17. The method of claim 16 wherein the functional modes comprise four functional modes comprising a bypass mode, the hardware accelerator pattern generator mode, a hardware accelerator memory mode and a hardware accelerator packet builder mode.

18. The method of claim 17 wherein the bypass mode further comprises generating all commands and data for coordinating testing of the plurality of DUTs using the tester processor and wherein the data generated by the tester processor in bypass mode comprises the protection information associated with the plurality of protection modes and sector data to fit each of the plurality of non-standard sector sizes.

19. The method of claim 17 wherein the hardware accelerator pattern generator mode comprises: generating all commands for coordinating testing of the plurality of DUTs using the tester processor; and using the hardware accelerator circuit to perform a step selected from the group comprising: generating all test pattern data, writing the test pattern data and comparing the test pattern data read from the plurality of DUTs, wherein the test pattern data comprises the protection information associated with the plurality of protection modes and sector data to fit each of the plurality of non-standard sector sizes.

20. The method of claim 17 , wherein, the

Assignees

• Advantest Corp

Inventors

• Malisic Srdjan
• Jones Michael
• Yuan Chi

Classifications

• G06F11/2733 Primary

  Test interface between tester and unit under test · CPC title

• G01R31/2834 Primary

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G01R31/31908 Primary

  Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns · CPC title

• G06F11/2257

  using expert systems · CPC title