Memory with bit line control

Patent metadata

Field	Value
Publication number	US-2016111142-A1
Application number	US-201514713648-A
Country	US
Kind code	A1
Filing date	May 15, 2015
Priority date	Oct 17, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal and coupled to a first select line to receive a first select signal. The first I/O circuit is configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal.

First claim

What is claimed is:

1 . A memory, comprising:
a first set of memory cells coupled between a first data line and a second data line; a first input/output (I/O) circuit configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on a first control signal and a first select signal.

2 . The memory of claim 1 , wherein the first I/O circuit is configured to precharge the first data line and the second data line to a predefined voltage when coupled to the first I/O circuit during the sleep mode,
wherein the first set of memory cells stores data during the sleep mode, and wherein the first set of memory cells are not accessed during the sleep mode.

3 . The memory of claim 1 , further comprising a second set of memory cells coupled between a third data line and a fourth data line.

4 . The memory of claim 3 , wherein the first I/O circuit configured to selectively decouple the third data line and the fourth data line from the first I/O circuit during the sleep mode based on the first control signal and the first select signal, and
wherein the third data line and the fourth data line are precharged to the predefined voltage when coupled to the first I/O circuit.

5 . The memory of claim 3 , further comprising a second I/O circuit configured to selectively decouple the third data line and the fourth data line from the second I/O circuit during the sleep mode based on the first select signal and the first control signal.

6 . The memory of claim 3 , further comprising a second I/O circuit configured to selectively decouple the third data line and the fourth data line from the second I/O circuit during the sleep mode based on a second select signal and the first control signal.

7 . The memory of claim 3 , wherein:
the first I/O circuit is configured to selectively decouple the third data line and the fourth data line from the first I/O circuit during the sleep mode based on a second select signal and the first control signal, the first I/O circuit being configured to precharge the third data line and the fourth data line to the predefined voltage during the sleep mode when coupled to the first I/O circuit.

8 . A memory, comprising:
a first set of memory cells coupled between a first data line and a second data line; a first input/output (I/O) circuit configured to selectively decouple the first I/O circuit from the first data line and the second data line during a sleep mode based on a first control signal and a first select signal; and a first feedback circuit coupled between the first data line and the second data line, the first feedback circuit being configured to precharge one of the first data line and the second data line to a predefined voltage during a sleep mode.

9 . The memory of claim 8 , wherein the first feedback circuit is configured to precharge the first data line if a leakage from the first data line exceeds a leakage from the second data line, and to precharge the second data line if the leakage from the second data line exceeds the leakage from the first data line.

10 . The memory of claim 9 , wherein the leakage of the first data line is based on content stored in the first set of memory cells, and the leakage of the second data line is based on content stored in the first set of memory cells.

11 . The memory of claim 9 , wherein the first feedback circuit comprises a pair of cross coupled transistors configured to cause one of the first data line or the second data line to be coupled with a voltage source corresponding to the predefined voltage.

12 . The memory of claim 9 ,
wherein the first set of memory cells stores data during the sleep state, and wherein the first set of memory cells are not accessed in the sleep state.

13 . The memory of claim 10 , further comprising:
a second set of memory cells coupled between a third data line and a second data line; and a second feedback circuit coupled between the third data line and the fourth data line, the second feedback circuit being configured to precharge one of the third data line or the fourth data line to the predefined voltage during the sleep mode.

14 . The memory of claim 13 , wherein the first I/O circuit is coupled to the third data line and the fourth data line, and
wherein the first I/O circuit is configured to selectively decouple the third data line and the fourth data line from the first I/O circuit based on the first select signal and the first control signal.

15 . The memory of claim 13 , further comprising a second I/O circuit configured to selectively decouple the third data line and the fourth data line from the second I/O circuit based on the first select signal and the first control signal.

16 . The memory of claim 13 , further comprising a second I/O circuit configured to selectively decouple the third data line and the fourth data line from the second I/O circuit based on the first control signal and a second select signal.

17 . The memory of claim 13 , wherein the first I/O circuit is configured to selectively decouple the third data line and the fourth data line from the first I/O circuit based on the first control signal and the second select signal.

18 . A method for managing power in a memory, comprising:
when a state of a first signal places a memory array in a sleep mode, enabling a charging circuit to charge a first set of data lines to a predefined voltage and disabling a second set of data lines to be in a floating state; and after activating the memory when a state of the first signal places the memory array in an active mode, charging the second set of data lines to the predefined voltage.

19 . The method of claim 18 , further comprising selecting the first set of data lines to charge based on a leakage current from memory cells coupled to the first set of data lines and a leakage current from memory cells coupled to the second set of data lines.

20 . The method of claim 19 , further comprising, when a state of the first signal places the memory array in the sleep mode, another charging circuit disables the second set of data lines.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yang Chen-Lin
• Lee Cheng Hung
• Liao Hung-Jen
• Lin Kao-Cheng
• Chang Jonathan Tsung-Yung
• Hsu Yu-Hao

Classifications

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title