Scalable low-latency storage interface

US10970003B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10970003-B2
Application numberUS-201916681316-A
CountryUS
Kind codeB2
Filing dateNov 12, 2019
Priority dateApr 12, 2017
Publication dateApr 6, 2021
Grant dateApr 6, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

First claim

Opening claim text (preview).

What is claimed is: 1. A system comprising: a host interface circuit to control communication between a set of virtual functions (VFs) and a media management system (MMS), the host interface circuit comprising: a command queue manager circuit to consolidate commands from the set of virtual functions, to dynamically allocate write buffers (WBs) from a set of available write buffers to the set of virtual functions using the commands, and to provide commands to the media management system; for each virtual function in the set of virtual functions: a virtual function submission queue circuit to manage a submission queue (SQ) for a respective virtual function from the set of virtual functions, and to receive a command from the respective virtual function comprising one or more submission queue entries (SQEs); and a virtual function write buffer list (WBL) circuit to manage a list of pending writes for the respective virtual function and to coordinate the one or more submission queue entries with allocated write buffers; and a write buffer access circuit to manage write buffer access for the set of virtual functions and to provide write data to the media management system by: receiving write data corresponding to a submission queue entry at an allocated write buffer; and providing write data from the allocated write buffer to the media management system, wherein each submission queue entry receives a certain number of allocated write buffers to provide write data to the media management system, and wherein the allocated write buffers from the set of available write buffers are free to receive additional write data after write data is provided to the media management system. 2. The system of claim 1 , wherein the virtual function submission queue circuit is further to determine if there are sufficient resources to hold the one or more submission queue entries in the submission queue, wherein, if there are sufficient resources to hold the one or more submission queue entries in the submission queue, the virtual function submission queue circuit is further to add the one or more submission queue entries to the submission queue, and wherein, if there are insufficient resources to hold the one or more submission queue entries in the submission queue, the command queue manager circuit is further to provide a command failure notification. 3. The system of claim 1 , wherein each submission queue entry uses a certain number of allocated write buffers to provide write data to the media management system, and wherein the allocated write buffers are free to receive additional write data after write data is provided to the media management system. 4. The system of claim 1 , further comprising a first allocated write buffer to receive a first logical block of data and to provide the first logical block of data to the media management system before all logical blocks of data associated with a first submission queue entry are provided to an allocated first plurality of write buffers. 5. The system of claim 1 , further comprising: a non-volatile memory controller, comprising: the host interface circuit; a communication interface; and the media management system, wherein the media management system is configured to be coupled to a non-volatile memory media device, wherein the host interface circuit is configured to control communication between a client device and the set of virtual functions using the communication interface, and wherein the communication interface comprises a peripheral component interconnect express (PCIe) interface. 6. The system of claim 1 , wherein the virtual function submission queue circuit is configured to receive the one or more submission queue entries and to receive write data using one or more base address registers (BARs) of a communication interface. 7. The system of claim 1 , wherein the command queue manager circuit is configured to receive a read command from the respective virtual function, to send the read command to the media management system, to receive read data from the media management system corresponding to the read command, and to provide read data to the respective virtual function. 8. A method to control communication between a set of virtual functions (VFs) and a media management system (MMS), the method comprising: consolidating commands from the set of virtual functions and dynamically allocating write buffers (WBs) from a set of available write buffers to the set of virtual functions using the commands using a command queue manager circuit; for each virtual function in the set of virtual functions: managing a submission queue (SQ) for a respective virtual function from the set of virtual functions, and receiving a command from the respective virtual function comprising one or more submission queue entries (SQEs), using a virtual function submission queue circuit; and managing a list of pending writes for the respective virtual function and coordinating the one or more submission queue entries with allocated write buffers using a virtual function write buffer list (WBL) circuit; and managing write buffer access for the set of virtual functions and providing write data to the media management system using a write buffer access circuit by: receiving write data corresponding to a submission queue entry at an allocated write buffer; and providing write data from the allocated write buffer to the media management system, wherein each submission queue entry receives a certain number of allocated write buffers to provide write data to the media management system, and wherein the allocated write buffers from the set of available write buffers are free to receive additional write data after write data is provided to the media management system. 9. The method of claim 8 , further comprising: determining if there are sufficient resources to hold the one or more submission queue entries in the submission queue; and if there are sufficient resources to hold the one or more submission queue entries in the submission queue, adding the one or more submission queue entries to the submission queue using the virtual function submission queue circuit; or if there are insufficient resources to hold the one or more submission queue entries in the submission queue, providing a command failure notification using the command queue manager circuit. 10. The method of claim 8 , further comprising: controlling communication between a client device and the set of virtual functions using a peripheral component interconnect express (PCIe) interface, wherein providing write data to the media management system comprises providing write data to a non-volatile memory device. 11. The method of claim 8 , wherein receiving the one or more submission queue entries and managing write buffer access for the set of virtual functions comprises using one or more base address registers (BARs) of a communication interface. 12. At least one non-transitory machine-readable medium comprising instructions that, when executed by processing circuitry of a host interface circuit, cause the host interface circuit to control communication between a set of virtual functions (VFs) and a media management system (MMS) by performing operations comprising: consolidating commands from the set of virtual functions; dynamically allocating write buffers (WBs) from a set of available write buffers to the set of virtual functions using the commands; for each virtual function in the set of virtual functions: managing a submission queue (SQ) for a respective virtual function from the set of virtual functions; receiving a command from the respective virtual function comprising one

Assignees

Inventors

Classifications

  • Latency reduction · CPC title

  • using buffers · CPC title

  • Data buffering arrangements · CPC title

  • with latency improvement · CPC title

  • G06F3/0659Primary

    Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

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Frequently asked questions

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What does patent US10970003B2 cover?
Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set …
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0659. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 06 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).