Storage device, a host system including the storage device, and a map table updating method of the host system

Patent metadata

Field	Value
Publication number	US-2016267016-A1
Application number	US-201614996562-A
Country	US
Kind code	A1
Filing date	Jan 15, 2016
Priority date	Mar 9, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

A host system includes a host device, a host buffer memory, and storage device. The host device includes a plurality of cores. The host buffer memory is configured to store a first command queue and a first map table, wherein each of the first command queue and the first map table corresponds to a first core of the cores. The storage device is configured to perform an input/output virtualization operation using the first core as a virtual core. The storage device uses the first command queue and the first map table during the input/output virtualization operation using the first core.

First claim

What is claimed is:

1 . A host system comprising:
a host device including a plurality of cores; a host buffer memory configured to store a first command queue and a first map table, wherein each of the first command queue and the first map table corresponds to a first core of the cores; and a storage device configured to perform an input/output virtualization operation using the first core as a virtual core, wherein the storage device uses the first command queue and the first map table during the input/output virtualization operation using the first core.

2 . The host system of claim 1 , wherein
the host device and the storage device communicate with each other through a virtualization interface that supports the input/output virtualization operation.

3 . The host system of claim 2 , wherein
the virtualization interface is at least one of nonvolatile memory express (NVMe), peripheral component interconnect express queuing interface (PQI), serial advanced technology attachment express (SATAe), or low latency interface (LLI).

4 . The host system of claim 1 , wherein
the first command queue includes a submission queue for storing a command request and a completion queue for storing a response of a result of the command request.

5 . The host system of claim 1 , wherein
the host device further includes a graph processing unit, and the host buffer memory further stores a second command queue and a second map table used for an input/output virtualization operation using the graphic processing unit.

6 . The host system of claim 1 , wherein
the host device further includes a modem processor performing a wired or wireless communication, and the host buffer memory further stores a third command queue and a third map table used for an input/output virtualization operation using the modem processor.

7 . The host system of claim 1 , further comprising:
a modem chip including a modem processor, wherein the modem chip is disposed outside of the host device, and the modem processor performs a wired or wireless communication, wherein the host buffer memory further stores a fourth command queue and a fourth map table used for an input/output virtualization operation using the modem processor.

8 . The host system of claim 1 , wherein
the storage device comprises: a virtualization interface circuit configured to communicate with the host device, and control the input/output virtualization operation; an address translation unit configured to support access of the storage device to the host buffer memory, set an address corresponding to an area of the host buffer memory, and provide the set address to a direct memory access circuit as a translated address; the direct memory access circuit configured to write or read data into or from the host buffer memory based on the translated address; and at least one processor configured to control an overall operation of the storage device.

9 . The host system of claim 8 , wherein
the virtualization interface circuit comprises: a physical function controller configured to control an input/output operation using the at least one processor of the storage device in a first command queue manner; and a plurality of virtual function controllers, each of which is configured to control an input/output virtualization operation using a corresponding one of the cores of the host device as a virtual core in a second command queue manner.

10 . The host system of claim 8 , wherein
the direct memory access circuit comprises: a write direct memory access circuit configured to support a data write operation of writing data into the host buffer memory; and a read direct memory access circuit configured to support a data read operation of reading data from the host buffer memory.

11 . The host system of claim 8 , wherein
the storage device further comprises: a buffer memory configured to store a portion of the first command queue and a portion of the first map table stored in the host buffer memory or to store data input/output during the input/output virtualization operation.

12 . A storage device comprising:
at least one nonvolatile memory device; and a memory controller configured to control the at least one nonvolatile memory device, wherein the memory controller comprises: an error correction circuit configured to correct an error of data output from the at least one nonvolatile memory device; a direct memory access circuit configured to directly access a processor, and to write data into an external host buffer memory; an address translation circuit configured to set an address corresponding to an area of the external host buffer memory according to a request of the direct memory access circuit; a host interface circuit configured to communicate with an external host device in a command queue manner, the host interface circuit including a physical function controller configured to control an input/output operation using the processor and a plurality of virtual function controllers, each of which is configured to control an input/output virtualization operation using a corresponding one of a plurality of cores of the external host device; and a nonvolatile memory interface circuit configured to perform interfacing with the at least one nonvolatile memory device, wherein the input/output virtualization operation includes translating a logical address into a physical address using a map table read from the host buffer memory.

13 . The storage device of claim 12 , further comprising:
a buffer memory configured to store a command queue and a portion of the map table of the host buffer memory, wherein the buffer memory is a static random access memory (SRAM).

14 . A method for updating a map table of a storage device, comprising:
receiving a write command; determining whether a map table needs to be updated when a write operation is performed according to the write command; reading the map table from an external host buffer memory using a direct memory access circuit when it is determined that the map table needs to be updated; and updating the read map table to at least one nonvolatile memory device.

15 . The method of claim 14 , wherein
the reading of the map table comprises: setting an address corresponding to an area of the host buffer memory in which the map table is stored, through an address translation unit.

16 . A storage host system comprising:
a host device including a first core and a host buffer memory controller controlling a host buffer memory; the host buffer memory configured to store first and second command queues, and first and second map tables, and a storage device including a memory device and a memory controller controlling the memory device, wherein the storage device performs an input/output operation using at least one processor of the memory controller, and the storage device performs an input/output virtualization operation using the first core of the host device as a virtual core, wherein the storage device uses the first command queue and the first map table during the input/output operation using the at least one processor, and wherein the storage device uses the second command queue and the second map table during the input/output virtualization operation using the first core.

17 . The storage host system of claim 16 , wherein the memory device is a nonvolatile memory device.

18 . The storage host system of claim 16 , wherein the memory controller further includes:
a direct memory access circuit configured t

Assignees

• Samsung Electronics Co Ltd

Inventors

• LEE Taehack
• Song Je-Hyuck

Classifications

• G06F13/1642

  with request queuing · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F9/455 Primary

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title