Scalable low-latency storage interface

Patent metadata

Field	Value
Publication number	US-2018300064-A1
Application number	US-201715485877-A
Country	US
Kind code	A1
Filing date	Apr 12, 2017
Priority date	Apr 12, 2017
Publication date	Oct 18, 2018
Grant date	—

Abstract

Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

First claim

What is claimed is:

1 . A system comprising:
a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS), the host interface circuit including:
a command queue manager circuit configured to consolidate commands from the set of VFs, to dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and to provide commands to the MMS;
for each VF in the set of VFs:
a VF submission queue circuit configured to manage a submission queue (SQ) for a respective VF from the set of VFs, and to receive a command from the respective VF, including one or more submission queue entries (SQEs); and
a VF write buffer list (WBL) circuit configured to manage a list of pending writes for the respective VF and to coordinate the one or more received SQEs with allocated WBs; and

a WB access circuit configured to manage WB access for the set of VFs and to provide write data to the MMS.

2 . The system of claim 1 , wherein the VF submission queue circuit is configured to determine if there are sufficient resources to hold the one or more received SQEs in the SQ,
wherein, if there are sufficient resources to hold the one or more received SQEs in the SQ, the VF submission queue circuit is configured add the one or more received SQEs to the SQ, and wherein, if there are insufficient resources to hold the one or more received SQEs in the SQ, the command queue manager circuit is configured to provide a command failure notification.

3 . The system of claim 1 , wherein each SQE requires a certain number of allocated WBs to provide write data to the MMS, and
wherein the allocated WBs are free to receive additional write data after write data is provided to the MMS.

4 . The system of claim 1 , wherein a first allocated WB is configured to receive initial write data corresponding to an SQE and to provide the initial write data to the MMS before receipt of all logical blocks of data associated with the SQE to the allocated WBs.

5 . The system of claim 1 , including:
a non-volatile memory (NVM) controller, including:
the host interface circuit;
a communication interface; and
the MMS,
wherein the MMS is configured to be coupled to a NVM media device, wherein the host interface circuit is configured to control communication between a client device and the set of VFs using a communication interface, and wherein the communication interface includes a peripheral component interconnect express (PCIe) interface.

6 . The system of claim 1 , wherein the VF submission queue circuit is configured to receive the one or more SQEs and to receive write data using one or more base address registers (BARS) of a communication interface.

7 . The system of claim 1 , wherein the command queue manager circuit is configured to receive a read command from the respective VF, to send the read command to the MMS, to receive read data from the MMS corresponding to the read command, and to provide read data to the respective VF.

8 . A method to control communication between a set of virtual functions (VFs) and a media management system (MMS), the method comprising:
consolidating commands from the set of VFs and dynamically allocating write buffers (WBs) from a set of available WBs to the set of VFs using the commands using a command queue manager circuit; for each VF in the set of VFs:
managing a submission queue (SQ) for a respective VF from the set of VFs, and receiving a command from the respective VF, including one or more submission queue entries (SQEs), using a VF submission queue circuit; and
managing a list of pending writes for the respective VF and coordinating the one or more received SQEs with allocated WBs using a VF write buffer list (WBL) circuit; and
managing WB access for the set of VFs and providing write data to the MMS using a WB access circuit.

9 . The method of claim 8 , including:
determining if there are sufficient resources to hold the one or more received SQEs in the SQ; and
if there are sufficient resources to hold the one or more received SQEs in the SQ, adding the one or more received SQEs to the SQ using the VF submission queue circuit; or
if there are insufficient resources to hold the one or more received SQEs in the SQ, providing a command failure notification using the command queue manager circuit.

10 . The method of claim 8 , wherein managing WB access for the set of VFs includes:
receiving write data corresponding to an SQE at an allocated WB; and providing write data from the allocated WB to the MMS, wherein each SQE requires a certain number of allocated WBs to provide write data to the MMS, and wherein the allocated WBs from the set of WBs are free to receive additional write data after write data is provided to the MMS.

11 . The method of claim 8 , including:
receiving initial write data corresponding to an SQE at a first allocated WB; and providing the initial write data from the allocated WB to the MMS after write data for the allocated WB is received, before the set of WBs receives all logical blocks associated with the SQE of the individual WB.

12 . The method of claim 8 , including:
controlling communication between a client device and the set of VFs using a peripheral component interconnect express (PCIe) interface, wherein providing write data to the MMS includes providing write data to a non-volatile memory (NVM) device.

13 . The method of claim 8 , wherein receiving the one or more SQEs and managing WB access for the set of VFs includes using one or more base address registers (BARS) of a communication interface.

14 . At least one machine-readable medium including instructions that, when executed by processing circuitry of a host interface circuit, cause the host interface circuit to control communication between a set of virtual functions (VFs) and a media management system (MMS), including to:
consolidate commands from the set of VFs; dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands; for each VF in the set of VFs:
manage a submission queue (SQ) for a respective VF from the set of VFs;
receive a command from the respective VF, including one or more submission queue entries (SQEs); and
coordinate the one or more received SQEs with allocated WBs; and
manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs.

15 . The at least one machine-readable medium of claim 14 , including instructions that, when executed by the processing circuitry of the host interface circuit, cause the host interface circuit to:
determine if there are sufficient resources to hold the one or more received SQEs in the SQ; and
if there are sufficient resources to hold the one or more received SQEs in the SQ, add the one or more received SQEs to the SQ; or
if there are insufficient resources to hold the one or more received SQEs in the SQ, provide a command failure notification.

16 . The at least one machine-readable medium of claim 14 , wherein the instructions that, when executed by the processing circuitry of the host interface circuit, cause the host interface circuit to manage WB access for the one or more VFs to the available WBs include instructions to:
receive write data corresponding to an SQE at an allocated WB; and provide write data from the allocated WB to the MMS, wherein each SQE requires a certain number of allocated WBs to provide write data to the MMS, and wherein the allocated WBs from the set of WBs are fre

Assignees

• Micron Technology Inc

Inventors

• Mcglaughlin Edward
• Tchapda Yves
• Marshall Stephen
• Bradshaw Samuel
• Reimers Niels

Classifications

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title