Semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10964618-B2
Application number	US-201916529331-A
Country	US
Kind code	B2
Filing date	Aug 1, 2019
Priority date	Nov 23, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A semiconductor package includes a first semiconductor chip, a second semiconductor chip attached to an upper surface of the first semiconductor chip, a silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip, and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and exposing an upper surface of the silicon heat-dissipation body.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip;
a second semiconductor chip attached to an upper surface of the first semiconductor chip;
a first silicon heat-dissipation body thermally connected to at least one of the first semiconductor chip and the second semiconductor chip; and
a molding member configured to surround the first semiconductor chip and the second semiconductor chip,
wherein the first silicon heat-dissipation body has an exposed upper surface with respect to the molding member, and
wherein the first silicon heat-dissipation body is not connected to any one of the first semiconductor chip and the second semiconductor chip included in the semiconductor package, by an electrically conductive interconnection.

2. The semiconductor package of claim 1 , wherein the first silicon heat-dissipation body is single-crystalline silicon or polycrystalline silicon.

3. The semiconductor package of claim 1 , wherein the first silicon heat-dissipation body is adhered to at least one of the first semiconductor chip and the second semiconductor chip by a die-attach film (DAF).

4. The semiconductor package of claim 3 , wherein the DAF comprises a thermal DAF including a thermally conductive filler.

5. The semiconductor package of claim 1 , wherein the first semiconductor chip is mounted as a flip-chip type on a package substrate.

6. The semiconductor package of claim 5 , wherein the second semiconductor chip is mounted on the first semiconductor chip such that an active surface of the second semiconductor chip faces the first silicon heat-dissipation body.

7. The semiconductor package of claim 6 , wherein the second semiconductor chip is mounted on the first semiconductor chip with a portion overhanging an edge of the first semiconductor chip to form an overhang portion of the second semiconductor chip.

8. The semiconductor package of claim 7 ,
wherein the overhang portion of the second semiconductor chip comprises a bonding pad, and
wherein the bonding pad of the overhang portion is electrically connected to the package substrate through a bonding wire.

9. The semiconductor package of claim 1 , wherein the first silicon heat-dissipation body is attached to the upper surface of the first semiconductor chip and vertically extends from the upper surface of the first semiconductor chip to an upper surface of the semiconductor package.

10. The semiconductor package of claim 1 ,
wherein the first silicon heat-dissipation body is attached to the upper surface of the first semiconductor chip, the first silicon heat-dissipation body vertically extending from the upper surface of the first semiconductor chip to an upper surface of the semiconductor package,
wherein the semiconductor package comprises a second silicon heat-dissipation body connected to an upper surface of the second semiconductor chip, the second silicon heat-dissipation body vertically extending from the upper surface of the second semiconductor chip to the upper surface of the semiconductor package, and
wherein upper surfaces of the first silicon heat-dissipation body and the second silicon heat-dissipation body form portions of the upper surface of the semiconductor package.

11. The semiconductor package of claim 10 ,
wherein the upper surface of the first silicon heat-dissipation body is substantially coplanar with the upper surface of the second silicon heat-dissipation body, and
wherein the surface area of the upper surface of the second silicon heat-dissipation body is larger than the surface area of the upper surface of the first silicon heat-dissipation body.

12. The semiconductor package of claim 10 , further comprising:
a plurality of memory chips directly adhered to the first semiconductor chip, the second semiconductor chip being one of the plurality of memory chips,
wherein the second silicon heat-dissipation body is formed on the plurality of memory chips.

13. The semiconductor package of claim 1 , wherein the first silicon heat-dissipation body is connected to an upper surface of the second semiconductor chip and configured to extend in a lateral direction over an upper surface of the first semiconductor chip.

14. The semiconductor package of claim 13 , further comprising a second silicon heat-dissipation body connected to the upper surface of the first semiconductor chip, the second silicon heat-dissipation body vertically extending from the upper surface of the first semiconductor chip to a lower surface of the first silicon heat-dissipation body.

15. The semiconductor package of claim 1 , wherein the first heat-dissipation body is metal and is connected to the upper surface of the first semiconductor chip, the first heat-dissipation body vertically extending from the upper surface of the first semiconductor chip to an upper surface of the semiconductor package.

16. The semiconductor package of claim 1 , comprising a first memory chip and a second memory chip on the first semiconductor chip with a path formed between the first memory chip and the second memory chip, the second semiconductor chip being one of the first memory chip and second memory chip,
wherein the first silicon heat-dissipation body includes a portion positioned along the path, and a first side surface of the first silicon heat-dissipation body extends to face at least three side surfaces the first memory chip and a second side surface of the first silicon heat-dissipation body extends to face at least three side surfaces the second memory chip.

17. The semiconductor package of claim 1 , comprising a first memory chip and a second memory chip, which are offset in a lateral direction and sequentially stacked on the first semiconductor chip, the second semiconductor chip being one of the first memory chip and second memory chip,
wherein the first silicon heat-dissipation body is connected to the upper surface of the first semiconductor chip and vertically extends from the upper surface of the first semiconductor chip to an upper surface of the semiconductor package, and
wherein at least a portion of the first silicon heat-dissipation body extends toward the first memory chip under the second memory chip.

18. A semiconductor package comprising:
a package substrate;
a logic chip mounted on the package substrate;
at least one memory chip on the logic chip, the at least one memory chip being formed on an upper surface of the logic chip;
a molding member configured to encapsulate the logic chip and the at least one memory chip; and
a silicon heat-dissipation body adhered to the upper surface of the logic chip, the silicon heat-dissipation body having at least one surface exposed with respect to the molding member to the outside of the semiconductor package.

19. The semiconductor package of claim 18 , wherein the silicon heat-dissipation body includes an upper surface forming at least a part of an upper surface of the semiconductor package.

20. An electronic system comprising:
a controller;
a memory configured to store data;
an interface circuit configured to transmit and receive data to and from an external device; and
a bus configured to connect the controller, the memory, and the interface circuit such that the controller, the memory, and the interface circuit communicate with each other,
wherein at least one of the controller and the memory comprises the semiconductor package of claim 1 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jang-Woo
• Oh Kyung-Suk
• Kong Yung-Cheol
• Park Woo-Hyun
• Shim Jong-Bo
• Cha Jae-Myeong

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title