Thermally conductive molding compound structure for heat dissipation in semiconductor packages

Patent metadata

Field	Value
Publication number	US-9960099-B2
Application number	US-201314076487-A
Country	US
Kind code	B2
Filing date	Nov 11, 2013
Priority date	Nov 11, 2013
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A method of forming a semiconductor package includes forming a thermal conductivity layer and attaching the thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the thermal conductivity layer.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a chip attached to a first substrate;
a thermal conductivity layer attached to the chip, wherein the thermal conductivity layer has interior sidewalls coupled to a lower interior surface of the thermal conductivity layer to define one or more recesses within an upper surface of the thermal conductivity layer facing away from the chip, and wherein the thermal conductivity layer provides a path through which heat generated from the chip is dissipated; and
a molding compound formed above the first substrate, the molding compound encapsulating the chip and the thermal conductivity layer.

2. The semiconductor package of claim 1 , further comprising:
an adhesive layer configured to attach the thermal conductivity layer to the chip.

3. The semiconductor package of claim 1 , further comprising:
a thermal interface material (TIM) contacting an opposite side of the thermal conductivity layer as the chip, wherein the TIM has a bottommost surface contacting the thermal conductivity layer and covering the one or more recesses, and wherein the molding compound vertically separates the bottommost surface from a second chip attached to the first substrate; and
a heat sink above the TIM.

4. The semiconductor package of claim 1 , further comprising:
a second substrate attached to the first substrate by one or more of a ball grid array, a land grid array, or a pin grid array.

5. The semiconductor package of claim 1 , wherein the thermal conductivity layer comprises a thermally conductive filler material having a filler material comprising one or more of metallic material, solder material, semiconductor material, carbon nanotubes, carbon fibers, or graphite.

6. The semiconductor package of claim 5 , wherein the thermally conductive filler material comprises between 70% and 95% of the thermal conductivity layer.

7. The semiconductor package of claim 5 , wherein the metallic material comprises one or more of aluminum (Al), copper (Cu), silver (Ag), gold (Au), AlN or Al 2 O 3 .

8. The semiconductor package of claim 5 , wherein the solder material comprises one or more of tin, lead, copper, antimony or silver.

9. The semiconductor package of claim 1 , wherein the thermal conductivity layer includes a substantially solid layer comprising one or more of copper or a copper alloy.

10. The semiconductor package of claim 1 , wherein the thermal conductivity layer includes one or more of a thermally conductive adhesive layer, the thermally conductive adhesive layer comprising one or more of silver (Ag), copper (Cu), gold (Au), aluminum (Al), carbon nanotubes, carbon fibers or graphite.

11. The semiconductor package of claim 1 , wherein the thermal conductivity layer includes a polymer having a conductive filler material.

12. The semiconductor package of claim 11 , wherein the conductive filler material includes one or more of AlN, SiC, carbon nanotubes, carbon fibers, graphite, graphene, and metal particles.

13. A semiconductor package, comprising:
a first chip attached to a first substrate;
a second chip attached to the first substrate;
a thermal conductivity layer attached to the first chip, the second chip being free from having the thermal conductivity layer attached, wherein the thermal conductivity layer has interior sidewalls coupled to a lower interior surface of the thermal conductivity layer to define one or more recesses within an upper surface of the thermal conductivity layer facing away from the first chip;
a molding compound over the first substrate, and surrounding the first chip, the second chip, and the thermal conductivity layer; and
wherein the thermal conductivity layer contacts a thermal interface material (TIM) overlying the molding compound.

14. The semiconductor package of claim 13 , wherein the thermal conductivity layer includes a thermally conductive adhesive layer comprising a metal material.

15. The semiconductor package of claim 13 , wherein the thermal conductivity layer includes a thermally conductive adhesive layer comprising carbon nanotubes.

16. The semiconductor package of claim 13 , further comprising:
an adhesive layer configured to attach the thermal conductivity layer to the first chip.

17. The semiconductor package of claim 13 , wherein the thermal conductivity layer comprises a thermally conductive filler material comprising one or more of a metallic material, a solder material, a semiconductor material, carbon nanotubes, carbon fibers, or graphite.

18. A semiconductor package, comprising:
a first chip attached to a first substrate and having a first height with respect to a surface of the first substrate;
a second chip attached to the first substrate and having a second height with respect to the surface of the first substrate;
a third chip attached to the first substrate and having a third height with respect to the surface of the first substrate;
a thermal conductivity layer attached to the first chip and to the second chip and having interior sidewalls coupled to lower interior surfaces of the thermal conductivity layer to define recesses within upper surfaces of the thermal conductivity layer disposed over and facing away from the first chip and the second chip, the third chip being free from having the thermal conductivity layer attached and the second chip having outermost sidewalls aligned along a first line with the thermal conductivity layer;
a molding compound over the first substrate, the first chip, the second chip, the third chip, and the thermal conductivity layer;
a thermal management device arranged over the molding compound, wherein the thermal management device has outermost sidewalls aligned along a second line with sidewalls of the molding compound and interior sidewalls defining one or more recesses within an upper surface of the thermal management device; and
wherein the first height of the first chip and the third height of the third chip are different.

19. The semiconductor package of claim 18 , further comprising:
a thermal interface material having a bottommost surface contacting the thermal conductivity layer and covering the one or more recesses, wherein the molding compound vertically separates the bottommost surface of the thermal interface material from the third chip.

20. The semiconductor package of claim 18 , wherein the first height and the second height are smaller than the third height.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tseng Chun-Hao
• Kuo Ying-Hao
• Yee Kuo-Chung

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/874

  On different surfaces · CPC title