Semiconductor wafer composed of single-crystal silicon with high gate oxide breakdown, and a process for the manufacture thereof

Patent metadata

Field	Value
Publication number	US-10961640-B2
Application number	US-201716469951-A
Country	US
Kind code	B2
Filing date	Dec 8, 2017
Priority date	Dec 15, 2016
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

Semiconductor wafers useful for NAND circuitry and having a front side, a rear side, a middle and a periphery, have an Nv region which extends from the middle to the periphery;
a denuded zone which extends from the front side to a depth of not less than 20 μm into the interior of the semiconductor wafer, where the density of vacancies in the denuded zone, determined by means of platinum diffusion and DLTS is not more than 1×10 13 vacancies/cm 3 ; a concentration of oxygen of not less than 4.5×10 17 atoms/cm 3 and not more than 5.5×10 17 atoms/cm 3 ; a region in the interior of the semiconductor wafer which adjoins the denuded zone and has nuclei which can be developed by means of a heat treatment into BMDs having a peak density of not less than 6.0×10 9 /cm 3 , where the heat treatment comprises heating the semiconductor wafer to a temperature of 800° C. over a period of four hours and to a temperature of 1000° C. over a period of 16 hours. The wafers are produced by a unique RTA treatment of Nv wafers.

First claim

The invention claimed is:

1. A semiconductor wafer comprising of single-crystal silicon, having a front side, a rear side, a middle and a periphery, comprising:
an Nv region which extends from the middle to the periphery;
a denuded zone which extends from the front side to a depth of not less than 20 μm into the interior of the semiconductor wafer, where the density of vacancies in the denuded zone, determined by means of platinum diffusion and DLTS is not more than 1×10 13 vacancies/cm 3 ;
a concentration of oxygen of not less than 4.5×10 17 atoms/cm 3 and not more than 5.5×10 17 atoms/cm 3 ;
a region in the interior of the semiconductor wafer which adjoins the denuded zone and has nuclei which are identifiable by developing with a heat treatment into BMDs, the BMDs having a peak density of not less than 5.5×10 9 /cm 3 , where the heat treatment comprises heating the semiconductor wafer to a temperature of 800° C. over a period of four hours and to a temperature of 1000° C. over a period of 16 hours.

2. The semiconductor wafer of claim 1 , wherein the peak density of BMDs is at a distance of not more than 100 μm from the front side of the semiconductor wafer.

3. The semiconductor wafer of claim 1 , wherein the average of the density of BMDs at depths of from 9 μm to 340 μm from the front side of the semiconductor wafer, from the middle to the periphery of the semiconductor wafer, satisfies the condition that the ratio D BMDmax /D BMDmin is not more than 1.4, where D BMDmax is the greatest density of BMDs and D BMDmin is the lowest density of BMDs.

4. The semiconductor wafer of claim 1 , wherein the size of BMDs at depths of from 9 μm to 340 μm from the front side of the semiconductor wafer, from the middle to the periphery of the semiconductor wafer, satisfies the condition that the ratio S BMDlarge /S BMDsmall is not more than 1.3, where S BMDlarge is the largest of the BMDs and S BMDsmall is the smallest of the BMDs.

5. A process for producing a semiconductor wafer comprising single-crystal silicon of claim 1 , which comprises, in this order
growing of a single crystal of silicon by the CZ method;
parting of at least one semiconductor wafer composed of single-crystal silicon from the single crystal, where the semiconductor wafer has a concentration of oxygen of not less than 4.5×10 17 atoms/cm 3 and not more than 5.5×10 17 atoms/cm 3 and consists entirely of Nv region;
treating the at least one semiconductor wafer in a first RTA treatment at a temperature in a first temperature range of not less than 1285° C. and not more than 1295° C. over a period of not less than 20 s and not more than 40 s in an atmosphere containing argon and oxygen;
chemically treating the semiconductor wafer by a treatment which comprises chemical removal of an oxide layer from a front side of the semiconductor wafer;
treating the at least one semiconductor wafer in a second RTA treatment at a temperature in a second temperature range of not less than 1160° C. and not more than 1185° C. over a period of not less than 15 s and not more than 30 s in an atmosphere containing argon and ammonia, and at a temperature in a third temperature range of not less than 1150° C. and not more than 1175° C. in an inert atmosphere over a period of not less than 20 s and not more than 40 s.

6. The process of claim 5 , wherein growing of the single crystal is carried out in an atmosphere containing argon and hydrogen.

7. The process of claim 5 , wherein a single crystal is grown at a pulling speed of not less than 0.5 mm/min and the single crystal has a diameter of at least 300 mm.

8. The process of claim 5 , wherein the RTA treatment in the third temperature range is carried out in an atmosphere of argon.

9. The process of claim 5 , wherein a heat treatment of the semiconductor wafer composed of single-crystal silicon is carried out after the RTA treatment in the third temperature range and the heating of the semiconductor wafer to a temperature of 800° C. is carried out over a period of 4 hours and the heating of the semiconductor wafer to a temperature of 1000° C. is carried out over a period of 16 hours.

10. The semiconductor wafer of claim 1 , wherein the concentration of oxygen is not less than 4.5×10 17 atoms/cm 3 and not more than 5.0×10 17 atoms/cm 3 .

11. A process for producing a semiconductor wafer comprising single-crystal silicon, which comprises, in this order
growing of a single crystal of silicon by the CZ method;
parting of at least one semiconductor wafer composed of single-crystal silicon from the single crystal, where the semiconductor wafer has a concentration of oxygen of not less than 4.5×10 17 atoms/cm 3 and not more than 5.5×10 17 atoms/cm 3 and consists entirely of Nv region;
treating the at least one semiconductor wafer in a first RTA treatment at a temperature in a first temperature range of not less than 1285° C. and not more than 1295° C. over a period of not less than 20 s and not more than 40 s in an atmosphere containing argon and oxygen;
chemically treating the semiconductor wafer by a treatment which comprises chemical removal of an oxide layer from a front side of the semiconductor wafer;
treating the at least one semiconductor wafer in a second RTA treatment at a temperature in a second temperature range of not less than 1160° C. and not more than 1185° C. over a period of not less than 15 s and not more than 30 s in an atmosphere containing argon and ammonia, and at a temperature in a third temperature range of not less than 1150° C. and not more than 1175° C. in an inert atmosphere over a period of not less than 20 s and not more than 40 s.

Assignees

• Siltronic Ag

Inventors

• Mueller Timo
• Gehmlich Michael
• Sattler Andreas

Classifications

• H10P36/20

  Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• C30B33/02

  Heat treatment (C30B33/04, C30B33/06 take precedence) · CPC title

• C30B33/005

  Oxydation · CPC title

• C30B29/06 Primary

  Silicon · CPC title