Power device with low gate charge and low figure of merit

Patent metadata

Field	Value
Publication number	US-10957791-B2
Application number	US-201916296760-A
Country	US
Kind code	B2
Filing date	Mar 8, 2019
Priority date	Mar 8, 2019
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell.

First claim

What is claimed is:

1. A device comprising a cell, wherein each cell comprises:
a body comprising a main top surface and a main bottom surface;
a gate on the main surface on the device having a first length;
a gate insulation layer over the gate having a second length at least twice as long as the first length, the gate insulation layer having a first portion directly over the gate and a second portion directly over the main top surface of the body;
a source contact on a side of the body proximate to the gate;
a source metal region over the gate insulation layer; and
a drain contact on the main bottom surface of the body,
wherein the body comprises an N-type epitaxial layer extending from the main top surface of the body to the main bottom surface of the body, a first P-type column disposed below the first portion of the gate insulation layer extending from the main top surface of body and only partially into the N-type epitaxial layer, and a second P-type column disposed below the second portion of the gate insulation layer extending from the main top surface of the body and only partially into the N-type epitaxial layer, and wherein the gate is asymmetrical with respect to the gate insulation layer.

2. The device of claim 1 , wherein the device comprises a plurality of substantially identical cells.

3. The cell of claim 1 , wherein the source contact is asymmetrical with respect to the gate insulation layer.

4. The cell of claim 1 , wherein the second length is at least three times as long as the first length.

5. The cell of claim 1 , wherein the gate comprises a minimum length gate.

6. The cell of claim 1 , wherein the gate comprises a polysilicon gate.

7. A device comprising a cell, wherein each cell comprises:
a body comprising a main top surface and a main bottom surface;
a gate on the main surface on the device having a first length;
a gate insulation layer over the gate having a second length at least twice as long as the first length, the gate insulation layer having a first portion directly over the gate and a second portion directly over the main top surface of the body;
a source contact on a side of the body proximate to the gate;
a source metal region over the gate insulation layer; and
a drain contact on the main bottom surface of the body,
wherein the body comprises an N-type epitaxial layer extending from the main top surface of the body to the main bottom surface of the body between a first P-type column below the first portion of the gate insulation layer and a second P-type column below the second portion of the gate insulation layer, and wherein the gate is asymmetrical with respect to the gate insulation layer.

8. The device of claim 7 , wherein the device comprises a plurality of substantially identical cells.

9. The cell of claim 7 , wherein the source contact is asymmetrical with respect to the gate insulation layer.

10. The cell of claim 7 , wherein the second length is at least three times as long as the first length.

11. The cell of claim 7 , wherein the gate comprises a minimum length gate.

12. The cell of claim 7 , wherein the gate comprises a polysilicon gate.

13. A device comprising a cell, wherein each cell comprises:
a body comprising a main top surface and a main bottom surface;
a gate on the main surface on the device having a first length;
a gate insulation layer over the gate having a second length at least twice as long as the first length, the gate insulation layer having a first portion directly over the gate and a second portion directly over the main top surface of the body;
a source contact on a side of the body proximate to the gate;
a source metal region over the gate insulation layer; and
a drain contact on the main bottom surface of the body,
wherein the body comprises an epitaxial layer extending from the main top surface of the body to the main bottom surface of the body between a first column below the first portion of the gate insulation layer and a second column below the second portion of the gate insulation layer, and wherein the first column is immediately adjacent to the source contact, and wherein the gate is asymmetrical with respect to the gate insulation layer.

14. The device of claim 13 , wherein the device comprises a plurality of substantially identical cells.

15. The cell of claim 13 , wherein the source contact is asymmetrical with respect to the gate insulation layer.

16. The cell of claim 13 , wherein the second length is at least three times as long as the first length.

17. The cell of claim 13 , wherein the gate comprises a minimum length gate.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Gao Yang

Classifications

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D62/156

  Drain regions of DMOS transistors · CPC title

• H10D62/152

  Source regions of DMOS transistors · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title