Manufacturing methods for accurately aligned and self-balanced superjunction devices

Patent metadata

Field	Value
Publication number	US-9647059-B2
Application number	US-201414298922-A
Country	US
Kind code	B2
Filing date	Jun 8, 2014
Priority date	Sep 27, 2011
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

First claim

We claim:

1. A semiconductor power device disposed in a semiconductor substrate supporting a drift region wherein the drift region comprising:
a plurality of epitaxial layers of alternating conductivity type stacking alternately in a vertical direction; and
a plurality of P and N vertical columns disposed alternately adjacent to each other over a lateral direction perpendicular to the vertical direction.

2. The semiconductor power device of claim 1 , wherein:
each of the epitaxial layers comprising a plurality of doped regions of a conductivity type opposite to a conductivity type of the epitaxial layer and a plurality of epitaxial regions of the same conductivity type of the epitaxial layers disposed adjacent to the doped regions.

3. The semiconductor power device of claim 2 , wherein:
the doped regions and the epitaxial regions of same conductivity type in each of the epitaxial layers are vertically aligned with each other for forming the P and N vertical columns.

4. The semiconductor power device of claim 1 , wherein:
each of the P and N columns comprises multiple evenly doped and diffused epitaxial regions of the same conductivity type vertically interconnected with each other.

5. The semiconductor power device of claim 4 , wherein:
each of the doped and diffused regions in each of the epitaxial layers having a convex sidewall boundary with a maximum lateral width located substantially in the center of the diffused region and a minimum width located at an interface between one of the epitaxial layers with another of the vertically stacked epitaxial layers.

6. The semiconductor power device of claim 4 , wherein:
each of the epitaxial regions in each of the epitaxial layers having a concave sidewall boundary with a minimum lateral width located substantially in the center of the epitaxial layers and a maximum lateral width at the interface between one of the epitaxial layers with another of the vertically stacked epitaxial layers.

7. The semiconductor power device of claim 6 , wherein:
the minimum lateral width of the doped and diffused region in each of the epitaxial layers being substantially the same as the maximum lateral width of the epitaxial region in the epitaxial layer of the same conductivity.

Assignees

• Guan Lingping
• Bobde Madhur
• Bhalla Anup
• Lee Yeeheng
• Chen John
• Ho Moses
• Alpha & Omega Semiconductor

Inventors

• Guan Lingping
• Bobde Madhur
• Bhalla Anup
• Lee Yeeheng
• Chen John
• Ho Moses

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/22

  using masks · CPC title

• H10D62/054

  by high energy implantations in bulk semiconductor bodies, e.g. forming pillars · CPC title