Power semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9627470-B2
Application number	US-201414301328-A
Country	US
Kind code	B2
Filing date	Jun 10, 2014
Priority date	Aug 9, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the n th layer is P n , P 1 <P n (n≧2).

First claim

What is claimed is:

1. A power semiconductor device comprising:
a first semiconductor region of a first conductivity type having a top surface;
second semiconductor regions formed in the first semiconductor region and being of a second conductivity type;
a well region formed above the second semiconductor regions and being of the second conductivity type; and
a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers extending upwardly from a lower portion of the device, the widest width of the second semiconductor region of the n th layer is P n , P 1 <P n (n≧2),
a trench is formed to extend from the well region to a portion of the first layer of the second semiconductor regions, and
a concentration of impurities in a portion of the second semiconductor region, positioned adjacently to the trench, is reduced toward the trench in a direction parallel to the top surface of the first semiconductor region.

2. The power semiconductor device of claim 1 , wherein the widest width of the second semiconductor region of the n th layer is P n , P n-1 <P n (n≧2).

3. The power semiconductor device of claim 1 , wherein when a concentration of impurities at a portion at which a concentration of second conductivity type impurities is the highest in the direction of height of the device in the second semiconductor region of the n-th layer is D n , D 1 <D n (n≧2).

4. The power semiconductor device of claim 1 , wherein when a concentration of impurities at a portion at which a concentration of second conductivity type impurities is the highest in the direction of height of the device in the second semiconductor region of the n th layer is D n , D n-1 <D n (n≧2).

5. The power semiconductor device of claim 1 , wherein the trench has a gradually tapered shape such that an upper portion of the trench is wider than a width of a lower portion of the trench.

6. The power semiconductor device of claim 1 , further comprising a gate contacting an upper surface of the source and well regions.

7. The power semiconductor device of claim 1 , further comprising a gate including a gate oxide and a poly gate covered by the gate oxide.

8. A power semiconductor device comprising:
a first semiconductor region of a first conductivity type having a top surface;
second semiconductor regions formed in the first semiconductor region and being of a second conductivity type;
a well region formed above the second semiconductor regions and being of the second conductivity type; and
a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion thereof in a direction of height of the device, wherein the power semiconductor device further comprises a trench extending through the well region and to a portion of the first layer of the second semiconductor region, and
wherein a concentration of impurities in a portion of the second semiconductor region, positioned adjacently to the trench, is reduced toward the trench in a direction parallel to the top surface of the first semiconductor region.

9. The power semiconductor device of claim 8 , wherein the trench has a width wider at an upper portion thereof than at a lower portion thereof.

10. The power semiconductor device of claim 9 , wherein the trench has a tapered shape or a stair shape.

11. The power semiconductor device of claim 8 , wherein the trench is filled with at least one of a second conductivity type material and silicon oxide.

12. A power semiconductor device comprising:
a first semiconductor region of a first conductivity type having a top surface;
second semiconductor regions formed in the first semiconductor region and of a second conductivity type;
a well region formed above the second semiconductor regions and of the second conductivity type; and
a source region formed in the well region and of the first conductivity type,
wherein the second semiconductor regions include 1 to n layers formed from a lower portion thereof in a direction of height of the device, a length of a longest gap, in a direction of width of the device, of a depletion region formed in the second semiconductor region of the nth layer is R., R1<R. (n>2), a trench is formed to extend from the well region to a portion of the first layer of the second semiconductor regions, and
a concentration of impurities in a portion of the second semiconductor region, positioned adjacently to the trench, is reduced toward the trench in a direction parallel to the top surface of the first semiconductor region.

13. The power semiconductor device of claim 12 , wherein the length of the longest gap, in the direction of width of the device, of the depletion region formed in the second semiconductor region of the n th layer is R n , R n-1 <R n (n≧2).

14. A power semiconductor device comprising:
a first semiconductor region of a first conductivity type having a top surface;
RESURF layers formed in the first semiconductor region and having second semiconductor regions and third semiconductor regions alternately formed in a direction of width of the device, the second semiconductor regions being of a second conductivity type and the third semiconductor regions being of the first conductivity type;
a well region formed above the second semiconductor regions and of the second conductivity type; and
a source region formed in the well region and of the first conductivity type, wherein the RESURF layers include 1 to n RESURF layers formed from a lower portion thereof in a direction of height of the device,
a length of a shortest portion, in the direction of width of the device, of the third semiconductor region formed in the nth RESURF layer is Q n , Q 1 >Q n (n≧2), a trench formed to extend from the well region to a portion of the first RESURF layer,
a trench is formed to extend from the well region to a portion of the first RESURF layer, and
a concentration of impurities in a portion of the second semiconductor region, positioned adjacently to the trench, is reduced toward the trench in a direction parallel to the top surface of the first semiconductor region.

15. The power semiconductor device of claim 14 , wherein the length of the shortest portion, in the direction of width of the device, of the third semiconductor region formed in the n th RESURF layer is Q n , Q n-1 >Q n (n≧2).

16. The power semiconductor device of claim 14 , wherein a concentration of impurities at a portion at which a concentration of second conductivity type impurities is the highest in the direction of height of the device in the second semiconductor region of the n th RESURF layer is D n , D 1 <D n (n≧2).

17. The power semiconductor device of claim 16 , wherein the concentration of impurities at a portion at which a concentration of second conductivity type impurities is the highest in the direction of height of the device in the second semiconductor region of the n th RESURF layer is D n , D n-1 <D n (n≧2).

18. A power semiconductor device comprising:
a first semiconductor region of a first conductivity type having a top surface;
second semiconductor regions formed in the first semiconductor region and being of a second conductivity type;
a well region formed above the second semiconductor regions and of the second conductivity type; and
a source region formed in the well region and of the first conductivity type,
wherein the second semiconductor regions include first to nth layers

Assignees

• Samsung Electro Mech

Inventors

• Song In Hyuk
• Park Jae Hoon
• Um Kee Ju
• Seo Dong Soo

Classifications

• H10D30/00

  Field-effect transistors [FET] (insulated-gate bipolar transistors H10D12/00) · CPC title

• H10D12/441

  Vertical IGBTs · CPC title

• H10D12/411

  Insulated-gate bipolar transistors [IGBT] · CPC title

• H10D12/01

  Manufacture or treatment · CPC title

• H10D64/60

  Electrodes characterised by their materials · CPC title