Multitier arrangements of integrated devices, and methods of forming sense/access lines

Patent metadata

Field	Value
Publication number	US-10957741-B2
Application number	US-201916400572-A
Country	US
Kind code	B2
Filing date	May 1, 2019
Priority date	May 1, 2019
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.

First claim

We claim:

1. An arrangement, comprising:
a first tier including a first set of memory cells on one side of a coupling region, and a second set of memory cells on an opposing side of the coupling region;
a first series of sense/access lines under the memory cells of the first and second sets, and electrically connected with the memory cells of the first and second sets;
a conductive interconnect within the coupling region of the memory tier;
a sense/access line of a second series extending across the memory cells of the first and second sets, and across the conductive interconnect; the sense/access line of the second series having a first region comprising a first composition, and having a second region comprising a second composition which is different than the first composition; the first region being over the memory cells of the first and second series and being electrically connected with the memory cells of the first and second series; the second region being over the conductive interconnect and being electrically coupled with the conductive interconnect with the first composition being absent from over at least a portion of the conductive interconnect; and
a second tier vertically offset from the first tier; the second tier comprising circuitry which is coupled with the conductive interconnect.

2. The arrangement of claim 1 wherein the circuitry of the second tier is CMOS circuitry.

3. An arrangement, comprising:
a first tier including a first set of memory cells on one side of a coupling region, and a second set of memory cells on an opposing side of the coupling region;
a first series of sense/access lines under the memory cells of the first and second sets, and electrically connected with the memory cells of the first and second sets;
a conductive interconnect within the coupling region of the memory tier;
a sense/access line of a second series extending across the memory cells of the first and second sets, and across the conductive interconnect; the sense/access line of the second series having a first region comprising a first composition, and having a second region comprising a second composition which is different than the first composition, the first composition including two or more materials, and the second composition including a subset of the materials of the first composition; the first region being over the memory cells of the first and second series and being electrically connected with the memory cells of the first and second series; the second region being over the conductive interconnect and being electrically coupled with the conductive interconnect; and
a second tier vertically offset from the first tier; the second tier comprising circuitry which is coupled with the conductive interconnect.

4. The arrangement of claim 3 wherein the second composition has higher conductivity than the first composition.

5. The arrangement of claim 4 wherein the first composition includes an upper layer over a lower layer, with the upper layer comprising one or more of Ta, Pt, Cu, W and Pd; and wherein the second composition comprises only the upper layer.

6. The arrangement of claim 4 wherein the first composition includes one or more of Ta, Pt, Cu, W and Pd over one or more of carbon, WSiN, WN and TiN; and wherein the second composition includes only the one or more of Ta, Pt, Cu, W and Pd.

Assignees

• Micron Technology Inc

Inventors

• Wei Lei
• Li Hongqi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10B63/80 Primary

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10B63/30

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H01L45/16

  Electricity · mapped topic