VFET device design for top contact resistance measurement

Patent metadata

Field	Value
Publication number	US-10957605-B2
Application number	US-201916592681-A
Country	US
Kind code	B2
Filing date	Oct 3, 2019
Priority date	Dec 15, 2017
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

The present invention provides VFET device designs for top contact resistance measurement. In one aspect, a method of forming a VFET test structure includes: etching fins in a substrate (for active and sensing devices); forming bottom source/drains at a base of the fins; forming a STI region that isolates the bottom source/drains of the active device from that of the sensing device; forming a gate surrounding each of the fins; forming top source/drains over the gate, wherein the top source/drains of the active device and that of the sensing device are merged; and forming contacts to i) the bottom source/drains of the active device, ii) the top source/drains of the active device, and iii) the bottom source/drains of the sensing device. A test structure formed by the method as well as techniques for use thereof for measuring contact resistance are also provided.

First claim

What is claimed is:

1. A vertical field effect transistor (VFET) contact resistance test structure, comprising:
fins patterned in a substrate, wherein at least a first one of the fins serves as a vertical fin channel of an active VFET device and at least a second one of the fins serves as a vertical fin channel of a sensing VFET device;
bottom source and drains at a base of the fins;
a gate surrounding each of the fins;
top source and drains over the gate, wherein the top source and drains of the active VFET device and the top source and drains of the sensing VFET device are merged; and
contacts comprising: i) a contact to the bottom source and drains of the active VFET device, ii) a contact to the top source and drains, and iii) a contact to the bottom source and drains of the sensing VFET device, wherein the contact to the top source and drains directly contacts only the top source and drains of the active VFET device to permit measurement of actual contact resistance for the active VFET device.

2. The VFET contact resistance test structure of claim 1 , further comprising:
a shallow trench isolation (STI) region in the substrate in between the at least one first fin and the at least one second fin that provides isolation of the bottom source and drains of the active VFET device from the bottom source and drains of the sensing VFET device.

3. The VFET contact resistance test structure of claim 1 , further comprising:
bottom spacers disposed on the bottom source and drains.

4. The VFET contact resistance test structure of claim 3 , wherein the bottom spacers comprise a material selected from the group consisting of: silicon dioxide (SiO 2 ), silicon carbon oxide (SiCO), silicon nitride (SiN), silicon boron carbon nitride (SiBCN), silicon oxycarbon nitride (SiOCN), silicon carbon nitride (SiCN), and combinations thereof.

5. The VFET contact resistance test structure of claim 1 , further comprising:
top spacers disposed on the gate.

6. The VFET contact resistance test structure of claim 5 , wherein the top spacers comprise a material selected from the group consisting of: SiN, SiBCN, and combinations thereof.

7. The VFET contact resistance test structure of claim 1 , wherein the bottom source and drains comprise a doped epitaxial material on the substrate at the base of the fins.

8. The VFET contact resistance test structure of claim 1 , the gate comprises:
a gate dielectric disposed on the fins; and
a gate conductor disposed on the gate dielectric.

9. The VFET contact resistance test structure of claim 8 , wherein the gate conductor comprises a workfunction-setting metal selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al)-containing alloys, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tungsten (W), and combinations thereof.

10. The VFET contact resistance test structure of claim 8 , wherein the gate dielectric comprises a high-κ material selected from the group consisting of: hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), and combinations thereof.

11. The VFET contact resistance test structure of claim 1 , further comprising:
a gate contact to the gate.

12. The VFET contact resistance test structure of claim 1 , wherein the top source and drains comprise a doped epitaxial material.

13. The VFET contact resistance test structure of claim 12 , wherein the doped epitaxial material is selected from the group consisting of: doped epitaxial silicon (Si), doped epitaxial germanium (Ge) and doped epitaxial silicon germanium (SiGe).

14. A VFET contact resistance test structure, comprising:
fins patterned in a substrate, wherein at least a first one of the fins serves as a vertical fin channel of an active VFET device and at least a second one of the fins serves as a vertical fin channel of a sensing VFET device;
bottom source and drains at a base of the fins;
a shallow trench isolation (STI) region in the substrate in between the at least one first fin and the at least one second fin that provides isolation of the bottom source and drains of the active VFET device from the bottom source and drains of the sensing VFET device;
a gate surrounding each of the fins;
top source and drains over the gate, wherein the top source and drains of the active VFET device and the top source and drains of the sensing VFET device are merged; and
contacts comprising: i) a contact to the bottom source and drains of the active VFET device, ii) a contact to the top source and drains, and iii) a contact to the bottom source and drains of the sensing VFET device, wherein the contact to the top source and drains directly contacts only the top source and drains of the active VFET device to permit measurement of actual contact resistance for the active VFET device.

15. The VFET contact resistance test structure of claim 14 , further comprising:
bottom spacers disposed on the bottom source and drains.

16. The VFET contact resistance test structure of claim 14 , further comprising:
top spacers disposed on the gate.

17. The VFET contact resistance test structure of claim 14 , wherein the bottom source and drains comprise a doped epitaxial material on the substrate at the base of the fins.

18. The VFET contact resistance test structure of claim 14 , the gate comprises:
a gate dielectric disposed on the fins; and
a gate conductor disposed on the gate dielectric.

19. The VFET contact resistance test structure of claim 14 , further comprising:
a gate contact to the gate.

20. The VFET contact resistance test structure of claim 14 , wherein the top source and drains comprise a doped epitaxial material selected from the group consisting of: doped epitaxial Si, doped epitaxial Ge and doped epitaxial SiGe.

Assignees

• IBM

Inventors

• Zhang Chen
• Liu Zuoguang

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title