Superconducting bump bond electrical characterization

Patent metadata

Field	Value
Publication number	US-10950778-B2
Application number	US-201916241661-A
Country	US
Kind code	B2
Filing date	Jan 7, 2019
Priority date	Jan 7, 2019
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

First claim

What is claimed is:

1. A bump bond superconductivity test structure comprising:
a first superconducting integrated circuit (IC) chip;
a second superconducting IC chip galvanically connected to the first chip by bump bonds;
galvanic connections to one of the bump bonds, the galvanic connections configured to provide a flux bias current vertically through the one of the bump bonds between the first and second chips; and
a DC SQUID comprising a loop that electrically includes at least two of the bump bonds,
wherein the galvanic connections and the one of the bump bonds are configured such that the only part of the DC SQUID loop through which the flux bias current flows is the one of the bump bonds.

2. The test structure of claim 1 , wherein the DC SQUID comprises two Josephson junctions arranged in parallel.

3. The test structure of claim 2 , wherein the two Josephson junctions are both fabricated in the second chip but are connected to each other on one side only within the first chip.

4. The test structure of claim 1 , further comprising test wiring connected to the DC SQUID via the first chip and configured to provide test signals to the DC SQUID from outside of a cold space when the test structure is in the cold space, and to receive, outside of the cold space, result signals from the DC SQUID.

5. The test structure of claim 1 , wherein the flux bias current modulates a critical current of the DC SQUID.

6. The test structure of claim 1 , wherein the galvanic connections to the DC SQUID are configured to provide a critical bias current to the DC SQUID.

7. The test structure of claim 6 , wherein the galvanic connections to the DC SQUID are further configured to provide a measurement of a voltage across the DC SQUID.

8. The test structure of claim 1 , wherein the DC SQUID electrically includes more than two of the bump bonds arranged in series, alternate series pairs of the bump bonds being connected to each other by galvanic connections in the first chip and in the second chip, respectively.

9. The test structure of claim 8 , wherein at least three of the galvanic connections are configured to provide a first flux bias current vertically through one of the bump bonds between the first and second chips, and the galvanic connections are further configured to provide a second flux bias current through a plurality of the bump bonds.

10. A device comprising:
two bump-bonded superconducting integrated circuits (ICs);
positive and negative bias and voltage measurement terminals in a first of the two ICs;
positive and negative flux bias terminals in the first IC;
a DC SQUID having a single loop that traverses both of the two ICs;
a first Josephson junction (JJ) of the DC SQUID in one of the two ICs, the first JJ connected between a first bump bond and a first node, the first bump bond electrically connecting the first IC and a second of the two ICs; and
a second JJ of the DC SQUID in one of the two ICs, the second JJ connected between a second bump bond and the first node, the second bump bond electrically connecting the first and second ICs,
wherein the DC SQUID loop comprises the first and second JJs, the first and second bump bonds, and the first node, and
wherein the only portion of the loop traversed by a current path between the positive and negative flux bias terminals is the first bump bond.

11. The device of claim 10 , further comprising:
a third bump bond, outside of the loop, electrically connecting the first and second ICs, and connected between the positive flux bias terminal and the first bump bond; and
a fourth bump bond, outside of the loop, electrically connecting the first and second chips, and connected between the positive bias and voltage measurement terminal and the first node.

Assignees

• Graninger Aurelius L
• Strand Joel D
• Stoutimore Micah John Atman
• Keane Zachary Kyle
• Hartman Jeffrey David
• Hackley Justin C
• Northrop Grumman Systems Corp

Inventors

• Graninger Aurelius L
• Strand Joel D
• Stoutimore Micah John Atman
• Keane Zachary Kyle
• Hartman Jeffrey David
• Hackley Justin C

Classifications

• H10W72/072

  of bump connectors · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W72/07231

  Techniques · CPC title