Inner spacers for gate-all-around semiconductor devices

Patent metadata

Field	Value
Publication number	US-10950731-B1
Application number	US-201916572679-A
Country	US
Kind code	B1
Filing date	Sep 17, 2019
Priority date	Sep 17, 2019
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member; and
a porous dielectric feature comprising silicon and nitrogen,
wherein the porous dielectric feature is sandwiched between the first and second semiconductor channel members,
wherein a density of the porous dielectric feature is smaller than a density of silicon nitride.

2. The semiconductor device of claim 1 , wherein a dielectric constant of the porous dielectric feature is between about 4.9 and about 5.2.

3. The semiconductor device of claim 1 , wherein the density of the porous dielectric feature is between about 2.1 g/cm 3 and about 2.3 g/cm 3 .

4. The semiconductor device of claim 1 , wherein a nitrogen content of the porous dielectric feature is between about 30% and about 40%.

5. The semiconductor device of claim 1 , wherein the porous dielectric feature further comprises carbon.

6. The semiconductor device of claim 5 , wherein a carbon content of the porous dielectric feature is between about 3% and about 8%.

7. A method of fabricating a semiconductor device, comprising:
providing a fin element that includes a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
forming a dummy gate structure over a channel region of the fin element;
etching a source/drain region of the fin element to expose sidewalls of the plurality of first semiconductor layers and sidewalls of the plurality of second semiconductor layers;
selectively and partially recessing exposed sidewalls of the plurality of second semiconductor layers to form a plurality of recesses;
depositing an inner spacer layer over the plurality of recesses using an organosilane precursor and a nitrogen-containing gas;
treating the inner spacer layer; and
etching back the inner spacer layer.

8. The method of claim 7 , wherein the depositing of the inner spacer layer comprises depositing the inner spacer layer using atomic layer deposition.

9. The method of claim 7 ,
wherein the organosilane precursor has a chemical formula Si (CH 2 )SiR x Cl y ,
wherein a sum of x and y (x+y) is equal to 6.

10. The method of claim 7 ,
wherein the organosilane precursor has a chemical formula Si (CH 2 ) 2 SiR x Cl y ,
wherein a sum of x and y (x+y) is equal to 4.

11. The method of claim 7 ,
wherein the organosilane precursor has a chemical formula Si (CH 3 ) x Cl y ,
wherein a sum of x and y (x+y) is equal to 4.

12. The method of claim 7 ,
wherein the organosilane precursor has a chemical formula Si (CH 2 ) 2 Si(CH 3 ) x Cl y ,
wherein x is at least 2,
wherein a sum of x and y (x+y) is equal to 6.

13. The method of claim 7 ,
wherein the organosilane precursor has a chemical formula SiH x (R1) y (R2) z ,
wherein R1 is a methyl group,
wherein R2 includes a methylamino group or a dimethylamino group,
wherein x is at least 1,
wherein z is at least 1
wherein a sum of x, y and z (x+y+z) is equal to 4.

14. The method of claim 7 , wherein the treating of the inner spacer layer comprises an anneal process, an ultraviolet (UV) curing process, or a plasma treatment process.

15. A method of fabricating a semiconductor device, comprising:
providing a fin element that includes a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
forming a dummy gate structure over a channel region of the fin element;
etching a source/drain region of the fin element to expose sidewalls of the plurality of first semiconductor layers and sidewalls of the plurality of second semiconductor layers,
selectively and partially recessing exposed sidewalls of the plurality of second semiconductor layers to form a plurality of recesses;
depositing an inner spacer layer comprising silicon and nitrogen;
treating the inner spacer layer; and
etching back the inner spacer layer to form a porous silicon nitride layer that is less dense than silicon nitride.

16. The method of claim 15 ,
wherein the depositing of the inner spacer layer comprises using a precursor,
wherein a molecule of the precursor comprises silicon and at least one alkyl group.

17. The method of claim 16 , wherein the molecule of the precursor further comprises nitrogen or a halide group.

18. The method of claim 15 , wherein the treating of the inner spacer layer comprises annealing the inner spacer layer at a temperature between about 350° C. and about 700° C. in an ambient comprising helium, argon, nitrogen, hydrogen, or a combination thereof.

19. The method of claim 15 , wherein the treating of the inner spacer layer comprises irradiating the inner spacer layer with an ultraviolet (UV) radiation at a temperature between about 150° C. and about 450° C. in an ambient comprising helium, argon, or nitrogen.

20. The method of claim 15 , wherein the treating of the inner spacer layer comprises contacting the inner spacer layer with a remotely generated plasma comprising helium, hydrogen, nitrogen, or argon at a temperature between room temperature and about 350° C.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Yu-Yun
• Yen Fu-Ting
• Chen Ting-Ting
• Lin Keng-Chu
• Perng Tsu-Hsiu

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/665

  Porous materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title