Semiconductor memory

Patent metadata

Field	Value
Publication number	US-10950630-B2
Application number	US-202016927309-A
Country	US
Kind code	B2
Filing date	Jul 13, 2020
Priority date	Sep 19, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

First claim

The invention claimed is:

1. A semiconductor memory comprising:
a memory chip comprising a first area, a second area, and a third area provided in this order in a first direction,
the first area comprising a first memory cell array that comprises first memory cells, a first bit line, and a first word line,
the third area comprising a second memory cell array that comprises second memory cells, a second bit line, and a second word line,
the second area comprising a contact electrically connected to one of the first and second word lines; and

a circuit chip attached to the memory chip and comprising a fourth area, a fifth area, and a sixth area provided in this order in the first direction,
the fourth area comprising a first sense amplifier electrically connected to the first bit line,
the sixth area comprising a second sense amplifier electrically connected to the second bit line,
the fifth area comprising a row decoder electrically connected to the contact;

wherein the first area and the fourth area overlap in a second direction crossing the first direction, and
the third area and the sixth area overlap in the second direction.

2. The memory of claim 1 , wherein
the first word line includes more than one first word line,
the first memory cell array further comprises a first stack of the more than one first word line and a first pillar extending through the first stack, each of intersections between the first pillar and the more than one first word line being configured as the first memory cell,
the second word line includes more than one second word line,
the second memory cell array further comprises a second stack of the more than one second word line and a second pillar extending through the second stack, each of intersections between the second pillar and the more than one second word line being configured as the second memory cell,
the circuit chip comprises a substrate on which the first and second sense amplifiers and the row decoder are located,
part of the first bit line is between the substrate and the more than one first word line, and
part of the second bit line is between the substrate and the more than one second word line.

3. The memory of claim 2 , wherein
the first memory cell array further comprises a first source line above the first stack, the first pillar comprising an upper portion contacting the first source line, and
the second memory cell array further comprises a second source line above the second stack, the second pillar comprising an upper portion contacting the second source line.

4. The memory of claim 1 , wherein
the circuit chip further comprises a seventh area next to the fourth area in a third direction crossing the first and second directions, the seventh area comprising a control circuit configured to control the first memory cell array, and
the first area and the seventh area overlap in the second direction.

5. The memory of claim 4 , wherein
the seventh area is next to the fifth area in the first direction.

6. The memory of claim 1 , wherein
the memory chip further comprises an eighth area next to the first area and the second area in a third direction crossing the first and second directions, and
the circuit chip further comprises a ninth area overlapping the eighth area in the second direction and comprising an input/output circuit.

7. The memory of claim 6 , further comprising:
a pad on the memory chip, the pad being electrically connected to the input/output circuit and overlapping the first area and the eighth area in the second direction.

8. A semiconductor memory comprising:
a memory chip comprising a first area, a second area, a third area, a fourth area, and a fifth area arranged in a first direction,
the second area comprising a first memory cell array that comprises first memory cells, a first bit line, and first word lines,
the fourth area comprising a second memory cell array that comprises second memory cells, a second bit line, and second word lines,
the first area comprising a first contact electrically connected to the first word line,
the fifth area comprising a second contact electrically connected to the second word line,
the third area comprising a third contact electrically connected to the first word line, a fourth contact electrically connected to the second word line, or both of the third contact and the fourth contact; and

a circuit chip attached to the memory chip and comprising a sixth area, a seventh area, an eighth area, a ninth area, and a tenth area overlapping the first area, the second area, the third area, the fourth area, and the fifth area, respectively, in a second direction crossing the first direction,
the seventh area comprising a first sense amplifier electrically connected to the first bit line,
the ninth area comprising a second sense amplifier electrically connected to the second bit line,
the sixth area comprising a first row decoder electrically connected to the first contact,
the tenth area comprising a second row decoder electrically connected to the second contact,
the eighth area comprising a third row decoder, a fourth row decoder electrically connected to the third contact, or both of the third decoder and the fourth row decoder.

9. The memory of claim 8 , wherein
the first memory cell array further comprises a first stack of the first word lines and a first pillar extending through the first stack of the first word lines, each of intersections between the first pillar and the first word lines being configured as the first memory cell,
the second memory cell array further comprises a second stack of the second word lines and a second pillar extending through the second stack of the second word lines, each of intersections between the second pillar and the second word lines being configured as the second memory cell,
the circuit chip comprises a substrate on which the first sense amplifier, the second sense amplifier, the first row decoder, and the second row decoder are located,
a part of the first bit line is between the substrate and the first word lines, and
a part of the second bit line is between the substrate and the second word lines.

10. The memory of claim 9 , wherein
the first memory cell array further comprises a first source line above the first stack of the first word lines, the first pillar comprising an upper portion contacting the first source line, and
the second memory cell array further comprises a second source line above the second stack of the second word lines, the second pillar comprising an upper portion contacting the second source line.

11. The memory of claim 8 , wherein
the circuit chip further comprises an eleventh area and a twelfth area,
the eleventh area being next to the seventh area in a third direction crossing the first and second directions, the eleventh area comprising a first control circuit configured to control the first memory cell array, the second area and the eleventh area overlapping in the second direction,
the twelfth area being next to the ninth area in the third direction and comprising a second control circuit configured to control the second memory cell array, the fourth area and the twelfth area overlapping in the second direction.

12. The memory of claim 11 , wherein
the eleventh area is next to the sixth area and the eighth area in the first direction, and
the twelfth area is next to the eighth area and the tenth area in the first direction.

13. The memory of claim 8 , wherein
the memory chip further comprises a thirteenth area next to the first to fifth areas in a third direction crossing the first and second directions, and
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Assignees

• Toshiba Memory Corp

Inventors

• Tagami Masayoshi
• Iijima Jun
• Katsumata Ryota
• Higashi Kazuyuki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/333

  Compression bonding · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/301

  Bonding techniques, e.g. hybrid bonding · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title