Coarse grain coherency

Patent metadata

Field	Value
Publication number	US-10949945-B2
Application number	US-202016872046-A
Country	US
Kind code	B2
Filing date	May 11, 2020
Priority date	Apr 9, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

First claim

What is claimed is:

1. An electronic device comprising:
a general-purpose processor including a first cache memory and a first coherency module; and
a general-purpose graphics processor including a second cache memory and a second coherency module, wherein the first coherency module and the second coherency module enable heterogeneous coherency between the first cache memory and the second cache memory, the heterogeneous coherency enabled at multiple cache line granularity; and
one or more memory controllers coupled with the general-purpose processor and the general-purpose graphics processor, the one or more memory controllers to enable communication with a memory module to store a superline directory table, wherein the superline directory table is to track ownership for a superline owned by the general-purpose processor and the general-purpose graphics processor, wherein the superline is a sub-page address region that spans multiple cache lines of the first cache memory and the second cache memory.

2. The electronic device as in claim 1 , wherein data storage for the first cache memory is managed at cache line granularity, coherence for sub-page shared virtual memory allocations cached by the first cache memory, and the second cache memory are managed at superline granularity.

3. The electronic device as in claim 2 , wherein the first cache memory is a level 3 cache memory.

4. The electronic device as in claim 3 , wherein the second cache memory is a last level cache coupled with the general-purpose processor and the general-purpose graphics processor.

5. The electronic device as in claim 4 , wherein the general-purpose graphics processor includes a superline ownership table to store a set of superlines owned by the general-purpose graphics processor, wherein the superline ownership table includes an entry for each superline in the set of superlines owned by the general-purpose graphics processor and each entry in the superline ownership table includes a superline tag and a coherency protocol status for the superline.

6. The electronic device as in claim 5 , wherein the coherency protocol status is one of modified, exclusive, shared, or invalid and each entry in the superline ownership table additionally includes a valid bit for each cache line within the superline.

7. The electronic device as in claim 1 , wherein the general-purpose graphics processor additionally includes a graphics processing compute block including multiple graphics multiprocessors.

8. The electronic device as in claim 7 , wherein multiple graphics multiprocessors are to process a workload including graphics or compute operations.

9. The electronic device as in claim 8 , wherein the workload is a heterogeneous workload including operations to be performed by the general-purpose graphics processing compute block and the general-purpose processor.

10. The electronic device as in claim 9 , wherein the operations of the workload are to access a unified memory address space and the unified memory address space includes system memory and graphics processor memory.

11. The electronic device as in claim 10 , wherein the general-purpose graphics processor is an add-in card connected to the general-purpose processor via a system bus and the add-in card includes the graphics processor memory.

12. A data processing system comprising:
a general-purpose processor including a first cache memory and a first coherency module;
a system bus coupled with the general-purpose processor; and
a general-purpose graphics processor coupled with general-purpose processor via the system bus, the general-purpose graphics processor including a second cache memory and a second coherency module, wherein the first coherency module and the second coherency module enable heterogeneous coherency between the first cache memory and the second cache memory, the heterogeneous coherency enabled at multiple cache line granularity; and
a memory module to store a superline directory table, wherein the superline directory table is to track ownership for a superline owned by the general-purpose processor and the general-purpose graphics processor, wherein the superline is a sub-page address region that spans multiple cache lines of the first cache memory and the second cache memory.

13. The data processing system as in claim 12 , wherein data storage for the first cache memory is managed at cache line granularity, coherence for sub-page shared virtual memory allocations cached by the first cache memory, and the second cache memory are managed at superline granularity.

14. The data processing system as in claim 13 , wherein the first cache memory is a level 3 cache memory.

15. The data processing system as in claim 14 , wherein the second cache memory is a last level cache coupled with the general-purpose processor and the general-purpose graphics processor.

16. The data processing system as in claim 15 , wherein the general-purpose graphics processor includes a superline ownership table to store a set of superlines owned by the general-purpose graphics processor, wherein the superline ownership table includes an entry for each superline in the set of superlines owned by the general-purpose graphics processor and each entry in the superline ownership table includes a superline tag and a coherency protocol status for the superline.

17. The data processing system as in claim 16 , wherein the coherency protocol status is one of modified, exclusive, shared, or invalid and each entry in the superline ownership table additionally includes a valid bit for each cache line within the superline.

18. The data processing system as in claim 12 , wherein the general-purpose graphics processor additionally includes a graphics processing compute block including multiple graphics multiprocessors.

19. The data processing system as in claim 18 , wherein multiple graphics multiprocessors are to process a workload including graphics or compute operations.

20. The data processing system as in claim 19 , wherein the workload is a heterogeneous workload including operations to be performed by the general-purpose graphics processing compute block and the general-purpose processor, wherein the operations of the workload are to access a unified memory address space including system memory and graphics processor memory.

Assignees

• Intel Corp

Inventors

• Ray Joydeep
• Koker Altug
• Valerio James A
• Puffer David
• Appu Abhishek R
• Junkins Stephen

Classifications

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06T1/60

  Memory management · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F2212/302

  In image processor or graphics adapter · CPC title