Inter-processor communication techniques in a multiple-processor computing platform

Patent metadata

Field	Value
Publication number	US-9626234-B2
Application number	US-201414570974-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Sep 20, 2010
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

First claim

The invention claimed is:

1. A device comprising:
a graphics processing unit (GPU) comprising:
a GPU cache configured to perform caching services for a shared memory space of a memory, the shared memory space being accessible by another processing unit; and
one or more processing modules configured to selectively use caching services of the GPU cache to execute at least one of a read operation or a write operation with respect to the shared memory space of the memory in response to receiving information specifying whether caching services should be used for executing at least one of read operations or write operations with respect to the shared memory space, wherein to selectively use the caching services of the GPU cache to execute the at least one of the read operation or the write operation with respect to the shared memory space of the memory, the one or more processing modules are configured to:
disable the caching services performed by the GPU cache for the shared memory space of the memory when the information specifying whether the caching services should be used specifies that an immediate mode should be enabled; and
enable a shared memory cache coherency mode for the GPU cache when the information specifying whether the caching services should be used specifies that the immediate mode should be enabled.

2. The device of claim 1 , wherein the one or more processing modules are configured to use the caching services of the GPU cache to execute the at least one of the read operation or the write operation with respect to the shared memory space of the memory in response to receiving information specifying that caching services should be used for executing the at least one of read operations or write operations with respect to the shared memory space, and to not use the caching services of the GPU cache to execute the at least one of the read operation or the write operation with respect to the shared memory space of the memory in response to receiving information specifying that caching services should not be used for executing the at least one of read operations or write operations with respect to the shared memory space.

3. The device of claim 1 , wherein the information specifying whether caching services should be used for executing the at least one of read operations or write operations with respect to the shared memory space comprises at least one of a read instruction or a write instruction that specifies whether a cached mode is enabled for the at least one of the read instruction or the write instruction.

4. The device of claim 1 , wherein the information specifying whether caching services should be used for executing the at least one of read operations or write operations with respect to the shared memory space comprises the immediate mode attribute of a memory object associated with the shared memory space, the immediate mode attribute specifying whether the immediate mode is enabled for the memory object.

5. The device of claim 1 , wherein the one or more processing modules comprise a GPU cache control module.

6. The device of claim 1 , wherein the one or more processing modules comprise a bus controller.

7. The device of claim 1 , wherein the GPU comprises a programmable shader unit.

8. A method comprising:
performing caching services for a shared memory space of a memory, the shared memory space being accessible by another processing unit; and
selectively using, with one or more processing modules of a graphics processing unit (GPU), caching services of a GPU cache to execute at least one of a read operation or a write operation with respect to the shared memory space of the memory in response to receiving information specifying whether caching services should be used for executing at least one of read operations or write operations with respect to the shared memory space, the GPU cache being included in the GPU, the GPU cache being configured to perform caching services for the shared memory space of the memory, wherein selectively using the caching services of the GPU cache to execute the at least one of the read operation or the write operation with respect to the shared memory space of the memory comprises:
disabling the caching services performed by the GPU cache for the shared memory space of the memory when the information specifying whether the caching services should be used specifies that an immediate mode should be enabled; and
enabling a shared memory cache coherency mode for the GPU cache when the information specifying whether the caching services should be used specifies that the immediate mode should be enabled.

9. The method of claim 8 , wherein selectively using the caching services of the GPU cache comprises:
using the caching services of the GPU cache to execute the at least one of the read operation or the write operation with respect to the shared memory space of the memory in response to receiving information specifying that caching services should be used for executing the at least one of read operations or write operations with respect to the shared memory space; and
not using the caching services of the GPU cache to execute the at least one of the read operation or the write operation with respect to the shared memory space of the memory in response to receiving information specifying that caching services should not be used for executing the at least one of read operations or write operations with respect to the shared memory space.

10. The method of claim 8 , wherein the information specifying whether caching services should be used for executing the at least one of read operations or write operations with respect to the shared memory space comprises at least one of a read instruction or a write instruction that specifies whether a cached mode is enabled for the at least one of the read instruction or the write instruction.

11. The method of claim 8 , wherein the information specifying whether caching services should be used for executing the at least one of read operations or write operations with respect to the shared memory space comprises an immediate mode attribute of a memory object associated with the shared memory space, the immediate mode attribute specifying whether an immediate mode is enabled for the shared memory object.

12. The method of claim 8 , wherein the one or more processing modules comprise a GPU cache control module.

13. The method of claim 8 , wherein the one or more processing modules comprise a bus controller.

14. The method of claim 8 , wherein the GPU comprises a programmable shader unit.

15. An apparatus comprising:
a graphics processing unit (GPU) comprising:
a GPU cache configured to perform caching services for a shared memory space of a memory, the shared memory space being accessible by another processing unit; and
means for selectively using caching services of the GPU cache to execute at least one of a read operation or a write operation with respect to the shared memory space of the memory in response to receiving information specifying whether caching services should be used for executing at least one of read operations or write operations with respect to the shared memory space, wherein the means for selectively using the caching services of the GPU cache to execute at least one of the read operation or the write operation with respect to the shared memory space of the memory comprises:
means for disabling the caching services performed by the GPU cache for the shared memory space of the memory when the information specifying whether the caching services should be used specifies that an immediate mode should be enabl

Assignees

• Qualcomm Inc

Inventors

• Bourd Alexei Vladimirovich
• Sharp Colin Christopher
• Garcia Garcia David Rigel
• Zhang Chihong

Classifications

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06T1/60

  Memory management · CPC title

• G06F9/544 Primary

  Buffers; Shared memory; Pipes · CPC title

• G06F9/54

  Interprogram communication · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title