Data sampler circuit with equalization function and method for sampling data

Patent metadata

Field	Value
Publication number	US-9621136-B1
Application number	US-201514939273-A
Country	US
Kind code	B1
Filing date	Nov 12, 2015
Priority date	Nov 12, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A data sampler circuit comprises a transconductance amplifier, a latch circuit, a current-to-voltage converter, and a negative resistance circuit. The transconductance amplifier has an input and an output. The latch circuit is coupled to the output of the transconductance amplifier. The current-to-voltage converter has an input coupled to the output of the transconductance amplifier, and an output for providing a feedback signal to the latch circuit. The negative resistance circuit is coupled to the output of the transconductance amplifier and provides equalization during both a sampling mode and a data latching mode. In one embodiment, the negative resistance circuit comprises a pair of cross-coupled transistors. A gain of the negative resistance circuit can be adjusted based on a pulse width of an input signal.

First claim

What is claimed is:

1. A data sampler circuit comprising: a transconductance amplifier having an input and an output; a latch circuit coupled to the output of the transconductance amplifier; a current-to-voltage converter having an input coupled to the output of the transconductance amplifier, and an output for providing a feedback signal to the latch circuit; and a negative resistance circuit coupled to the output of the transconductance amplifier, a control circuit having an input coupled to the output of the current-to-voltage converter, and a output for providing a control signal to the variable gain negative resistance circuit.

2. The data sampler circuit of claim 1 , wherein the transconductance amplifier comprises a differential pair of transistors having control electrodes coupled to receive a differential signal.

3. The data sampler circuit of claim 1 , wherein the negative resistance circuit comprises a pair of cross-coupled transistors.

4. The data sampler circuit of claim 1 , wherein the negative resistance circuit further comprises a gain compensation circuit for varying a gain of the negative resistance circuit in response to a control signal.

5. The data sampler circuit of claim 1 , wherein the transconductance amplifier comprises:
a first current source having a first terminal coupled to a first power supply terminal, and a second terminal;
a second current source having a first terminal coupled to the first power supply terminal, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the first current source, a control electrode for receiving a first input signal, and a second current electrode;
a second transistor having a first current electrode coupled to the second terminal of the second current source, a control electrode for receiving a second input signal, and a second current electrode coupled to the second current electrode of the first transistor; and
a third transistor having a first current electrode coupled to the second current electrodes of the first and second transistors, a control electrode for receiving a first clock signal, and a second current electrode.

6. The data sampler circuit of claim 5 , wherein the latch circuit comprises:
a fourth transistor having a first current electrode coupled to the first current electrode of the first transistor, a control electrode, and a second current electrode;
a fifth transistor having a first current electrode coupled to the first current electrode of the second transistor, a control electrode, and a second current electrode coupled to the second current electrode of the fourth transistor; and
a sixth transistor having a first current electrode coupled to the second current electrodes of the fourth and fifth transistors, a control electrode for receiving a second clock signal, and a second current electrode.

7. The data sampler circuit of claim 6 , wherein the negative resistance circuit comprises:
a seventh transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the fourth transistor;
a first capacitor having a first plate electrode coupled to the control electrode of the seventh transistor, and a second plate electrode coupled to the first current electrode of the fifth transistor;
an eighth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the fifth transistor;
a second capacitor having a first plate electrode coupled to the control electrode of the eighth transistor, and a second plate electrode coupled to the first current electrode of the fourth transistor;
a first variable resistor having a first terminal coupled to receive a bias voltage, a control terminal for receiving a control signal, and a second terminal coupled to the control electrode of the seventh transistor; and
a second variable resistor having a first terminal coupled to receive the bias voltage, a control terminal for receiving the control signal, and a second terminal coupled to the control electrode of the eighth transistor.

8. The data sampler circuit of claim 7 , wherein the current-to-voltage converter further comprises:
a third current source having a first terminal coupled to the first power supply voltage terminal, and a second terminal;
a fourth current source having a first terminal coupled to the first power supply voltage terminal, and a second terminal;
a ninth transistor having first current electrode coupled to the second terminal of the third current source, a control electrode coupled to the first current electrode of the first transistor, and a second current electrode;
a first resistor having a first terminal coupled to the control electrode of the ninth transistor, and a second terminal coupled to the first current electrode of the ninth transistor;
a tenth transistor having a first current electrode coupled to the second terminal of the fourth current source, a control electrode coupled to the first current electrode of the second transistor, and a second current electrode coupled to the second current electrode of the ninth transistor; and
a second resistor having a first terminal coupled to the control electrode of the tenth transistor, and a second terminal coupled to the first current electrode of the tenth transistor.

9. The data sampler circuit of claim 1 , wherein the data sampler circuit is one of a plurality of data sampler circuits in a receiver circuit.

10. A receiver comprising:
an amplifier coupled to a channel for receiving serial data signals; and
a plurality of data samplers coupled to the amplifier, each of the plurality of data samplers comprising:
a transconductance amplifier having an input and an output;
a latch circuit coupled to the output of the transconductance amplifier;
a current-to-voltage converter having an input coupled to the output of the transconductance amplifier, and an output for providing a feedback signal to the latch circuit; and
a variable gain negative resistance circuit coupled to the output of the transconductance amplifier, the variable gain negative resistance circuit for providing tunable equalization for the receiver;

a control circuit having an input coupled to the output of the current-to-voltage converter, and a output for providing a control signal to the variable gain negative resistance circuit.

11. The receiver of claim 10 further comprising a channel comprises a transmission line.

12. The receiver of claim 10 , wherein the transconductance amplifier comprises:
a first current source having a first terminal coupled to a first power supply terminal, and a second terminal;
a second current source having a first terminal coupled to the first power supply terminal, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the first current source, a control electrode for receiving a first input signal, and a second current electrode;
a second transistor having a first current electrode coupled to the second terminal of the second current source, a control electrode for receiving a second input signal, and a second current electrode coupled to the second current electrode of the first transistor; and
a third transistor having a first current electrode coupled to the second current electrodes of the first and second transistors, a control electrode for receiving a first clock signal, and a second current electrode.

13. The receiver

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Chang Kevin Yi Cheng

Classifications

• H03K3/35613 Primary

  the input circuit having a differential configuration · CPC title

• H04B1/123

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03K3/356139 Primary

  with synchronous operation · CPC title