Zero if transmitter with decoupling between mixer and programmable gain stage

Patent metadata

Field	Value
Publication number	US-10944361-B2
Application number	US-201916274519-A
Country	US
Kind code	B2
Filing date	Feb 13, 2019
Priority date	Nov 30, 2018
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

A system includes a Zero IF transmitter having a mixer and a programmable gain stage. The Zero IF transmitter also includes an intermediate stage between the mixer and the programmable gain stage, wherein the intermediate stage is configured to decouple the mixer and the programmable gain stage.

First claim

What is claimed is:

1. A system, comprising:
a Zero IF transmitter having:
a mixer having inputs and outputs;

an intermediate stage having inputs and an output, wherein the inputs of the intermediate stage are coupled to the outputs of the mixer; and
a programmable gain stage having an input and an output wherein the input of the programamble gain stage is coupled to the output of the intermediate stage;
wherein the intermediate stage comprises a noise reduction circuit coupled to the intermediate stage inputs;
wherein the noise reduction circuit comprises passive components; and
wherein the passive components include an inductor for each intermediate stage input wherein each inductor is coupled between a decoupling circuit and a ground node.

2. A system, comprising:
a Zero IF transmitter having:
a mixer having inputs and outputs;

an intermediate stage having inputs and an output, wherein the inputs of the intermediate stage are coupled to the outputs of the mixer; and
a programmable gain stage having an input and an output wherein the input of the programmable gain stage is coupled to the output of the intermediate stage;
wherein the intermediate stage comprises a first decoupling circuit with a common gate structure and a second decoupling circuit with a common gate structure.

3. A system, comprising:
a Zero IF transmitter having:
a mixer having inputs and outputs;

an intermediate stage having inputs and an output, wherein the inputs of the intermediate stage are coupled to the outputs of the mixer; and
a programmable gain stage having an input and an output wherein the input of the programmable gain stage is coupled to the output of the intermediate stage;
wherein the intermediate stage comprises:
a first decoupling circuit coupled to a first set of intermediate stage inputs; and
a second decoupling circuit coupled to a second set of intermediate stage inputs.

4. The system of claim 3 , wherein the first decoupling circuit comprises:
a first transistor; and
a second transistor, wherein a first current terminal of the first transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the first transistor is coupled to a first mixer output, and wherein a control terminal of the first transistor is coupled to the second current terminal of the second transistor via a first capacitor, and
wherein a first current terminal of the second transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the second transistor is coupled to a second mixer output, and wherein a control terminal of the second transistor is coupled to the second current terminal of the first transistor via a second capacitor.

5. The system of claim 4 , wherein the second decoupling circuit comprises:
a third transistor; and
a fourth transistor, wherein a first current terminal of the third transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the third transistor is coupled to a third mixer output, and wherein a control terminal of the third transistor is coupled to the second current terminal of the fourth transistor via a third capacitor, and
wherein a first current terminal of the fourth transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the fourth transistor is coupled to a fourth mixer output, and wherein a control terminal of the fourth transistor is coupled to the second current terminal of the third transistor via a fourth capacitor.

6. A system, comprising:
a Zero IF transmitter having:
a mixer having inputs and outputs;

an intermediate stage having inputs and an output, wherein the inputs of the intermediate stage are coupled to the outputs of the mixer; and
a programmable gain stage having an input and an ouptut wherein the input of the programmable gain stage is coupled to the ouptut of the intermediate stage;
wherein the intermediate stage is configured to prevent dependency of I-Q mismatch and local oscillator leakage on the programmable gain stage.

7. A Zero IF transmitter circuit, comprising:
a mixer having inputs and outputs;
an intermediate stage having inputs and an ouput, wherein the inputs of the intermediate stage are coupled to the outputs of the mixer; and
a programmable gain stage having an input and an output wherein the input of the programmable gain stage is coupled to the output of the intermediate stage;
wherein the intermediate stage comprises a noise reduction circuit coupled to the mixer outputs; and
wherein the noise reduction circuit comprises an inductor for each intermediate stage input; wherein each inductor is coupled between the decoupling circuit and a ground node.

8. A Zero IF transmitter circuit, comprising:
a mixer having inputs and outputs;
an intermediate stage having inputs and an output, wherein the inputs of the intermediate stage are coupled to the outputs of the mixer; and
a programmable gain stage having an input and an output wherein the input of the programmable gain stage is coupled to the output of the intermediate stage;
wherein the decoupling circuit has a common gate structure.

9. A Zero IF transmitter circuit, comprising:
a mixer having inputs and outputs;
an intermediate stage having inputs and an output, wherein the inputs of the intermediate stage are coupled to the outputs of the mixer; and
a programmable gain stage haivng an input and an output wherein the input of the programmable gain stage is coupled to the output of the intermediate stage;
wherein the intermediate stage comprises a decoupling circuit;
wherein the intermediate stage comprises:
a first decoupling circuit coupled to a first set of intermediate stage inputs; and
a second decoupling circuit coupled to a second set of intermediate stage inputs.

10. The Zero IF transmitter circuit of claim 9 , wherein the first decoupling circuit comprises:
a first transistor; and
a second transistor, wherein a first current terminal of the first transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the first transistor is coupled to a first mixer output, and wherein a control terminal of the first transistor is coupled to the second current terminal of the second transistor via a first capacitor, and
wherein a first current terminal of the second transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the second transistor is coupled to a second mixer output, and wherein a control terminal of the second transistor is coupled to the second current terminal of the first transistor via a second capacitor.

11. The Zero IF transmitter circuit of claim 10 , wherein the second decoupling circuit comprises:
a third transistor; and
a fourth transistor, wherein a first current terminal of the third transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the third transistor is coupled to a third mixer output, and wherein a control terminal of the third transistor is coupled to the second current terminal of the fourth transistor via a third capacitor, and
wherein a first current terminal of the fourth transistor is coupled to the output of the intermediate stage, wherein a second current terminal of the fourth transistor is coupled to a fourth mixer output, and wherein a control terminal of the fourth transistor is coupled to the second current terminal of the third transistor via a fourth capacitor.

12. A Zero IF transmitter circuit, comprising:
a mixer having inputs and outputs;
an intermediate stage having inputs and an

Assignees

• Texas Instruments Inc

Inventors

• Sharma Rahul
• Venkataraman Jagannathan
• Miglani Eeshan
• Oswal Sandeep Kesrimal

Classifications

• H03C2200/0058

  Quadrature arrangements · CPC title

• H04B1/0028

  wherein the AD/DA conversion occurs at baseband stage · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H03C1/60

  with one sideband wholly or partially suppressed · CPC title

• H03C1/06 Primary

  Modifications of modulator to reduce distortion, e.g. by feedback, and clearly applicable to more than one type of modulator · CPC title